gem5 - gem5

Age	Commit message (Expand)	Author
2011-12-15	ARM: Update config files for Android/BBench images available on website.	Anthony Gutierrez
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-10-19	ARM: Fix small bug in config script that prevents android from booting	Ali Saidi
2011-08-19	ARM: Add some MP regressions and clean up the disk images and kernels a bit	Ali Saidi
2011-08-19	ARM: Add VExpress_E support with PCIe to gem5	Ali Saidi
2011-08-19	ARM: Add support for Versatile Express boards	Ali Saidi
2011-05-23	config: revamp x86 config to avoid appending to SimObjectVectors	Steve Reinhardt
2011-05-23	configs: missed spot progress-interval change	Korey Sewell
2011-05-20	configs: cleanup redundant/unused options	Korey Sewell
2011-05-04	ARM: Configure bootloader parameters	Ali Saidi
2011-04-20	python: fix another bug from changes to main.py	Nathan Binkert
2011-04-04	ARM: Include IDE/CF controller by default in PBX model.	Ali Saidi
2011-04-04	Sim: Fix Simulation.py to allow more than 1 core for standard switching.	Anthony Gutierrez
2011-03-17	ARM: Bare metal system should have 256MB of RAM.	Ali Saidi
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-02-24	Configs: Explicitly import env in Benchmarks.py	Gabe Black
2011-02-23	ARM: Clarifies creation of Linux and baremetal ARM systems.	Ali Saidi
2011-02-23	configs: cache: add cache line size option	Korey Sewell
2011-02-23	configs: set default cache params	Korey Sewell
2011-02-11	VNC: Add VNC server to M5	Ali Saidi
2011-02-08	config: fixed minor bug connecting dma devices to ruby	Brad Beckmann
2011-02-07	X86, Config: Move the setting of work count options to a separate function.	Gabe Black
2011-02-06	m5: added work completed monitoring support	Brad Beckmann
2011-02-06	ruby: x86 fs config support	Brad Beckmann
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-02-02	X86: Change how the default disk image gets set up.	Gabe Black
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
2010-11-17	Config: Change misleading "cycle" message to say "tick".	Gabe Black
2010-11-15	ARM: Add support for a dumb IDE controller	Ali Saidi
2010-11-08	Mem: Finish half-baked support for mmaping file in physmem.	Ali Saidi
2010-08-24	config: fixed ruby dma device connections	Brad Beckmann
2010-08-23	ARM: Add configuration for Linux/Full System	Ali Saidi
2010-08-20	ruby: Reduced ruby latencies	Brad Beckmann
2010-08-20	config: reorganized how ruby specifies command-line options	Brad Beckmann
2010-08-17	misc: add some AMD copyright notices	Steve Reinhardt
2010-08-17	sim: fold checkpoint restore code into instantiate()	Steve Reinhardt
2010-08-17	configs: clean up checkpoint code in Simulation.py	Steve Reinhardt
2010-08-17	sim: make Python Root object a singleton	Steve Reinhardt
2010-08-08	None, not none	Nathan Binkert
2010-07-05	util: add a script for testing checkpointing	Steve Reinhardt
2010-06-02	ARM: fix sizes of structs for ARM Linux	Ali Saidi
2010-04-18	config: fix assertion for x86 in FSConfig.py	Nathan Binkert
2010-03-21	ruby: Reorganized Ruby topology and protocol files	Brad Beckmann
2010-03-21	ruby: Adds configurable bit selection for numa mapping	Brad Beckmann
2010-03-21	ruby: Ruby support for sparse memory	Brad Beckmann
2010-03-21	ruby: fixed how ruby_fs creates phsyical memory	Brad Beckmann
2010-02-25	configs: pull out cache configuration code from se.py and fs.py.	Lisa Hsu
2010-01-29	ruby: Converted Garnet to M5 configuration	Brad Beckmann
2010-01-29	ruby: Added a mesh topology	Brad Beckmann
2010-01-29	ruby: MOESI_CMP_token updates to use the new config system	Brad Beckmann