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2019-03-20invisispec-1.0 configsIru Cai
2018-10-19config: add --param to fs.py, se.py and fs_bigLITTLE.pyCiro Santilli
The option allows to set SimObject params from the CLI. The existing config scripts have a large number of options that simply set a single SimObject parameter, and many still are not exposed. This commit allows users to pass arbitrary parameters from the command line to prevent the need for this kind of trivial option. Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944 Reviewed-on: https://gem5-review.googlesource.com/c/12985 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-08dev, arm: remove the RealViewEB platformCiro Santilli
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it. Furthermore, trying to use it fails with: object 'RealViewEB' has no attribute 'pci_host' and the last commit in the class happened two years ago, which indicates that no one has been using it. Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12config, dev-arm: Fix UART handling baremetal modeCiro Santilli
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform due to inconsistent UART naming with error message: AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart' Consistently name keep all UARTs in the Arm platforms in a vector named 'uart' or as a single device named 'uart'. Update the configuration scripts to reflect the fact that 'uart' can be a vector. Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12473 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-03config: Move KVM CPU checking to CpuConfig helper moduleAndreas Sandberg
Both se.py and fs.py need to check if a CPU is a KVM CPU. This is somewhat involved since CPUs can be disabled at compile time. Enable better code reuse by moving it to the CpuConfig module. Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12418 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17configs: Always exit with code 0Jason Lowe-Power
Update simulation.py to always exit with code 0 assuming the simulation exits normally. If the running application has a return code that is non zero, then print the return code before exiting. Change-Id: I1983985d50311627574d4364b32ee961ae88e003 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4880
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-03-22mem-cache: Split array indexing and replacement policies.Daniel R. Carvalho
Replacement policies (LRU, Random) are currently considered as array indexing methods, but have completely different functionalities: - Array indexers determine the possible locations for block allocation. This information is used to generate replacement candidates when conflicts happen. - Replacement policies determine which of the replacement candidates should be evicted to make room for new allocations. For this reason, they were split into different classes. Advantages: - Easier and more straightforward to implement other replacement policies (RRIP, LFU, ARC, ...) - Allow easier future implementation of cache organization schemes As now we can't assure the use of sets, the previous way to create a true LRU is not viable. Now a timestamp_bits parameter controls how many bits are dedicated for the timestamp, and a true LRU can be achieved through an infinite number of bits (although a few bits suffice in practice). Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda Reviewed-on: https://gem5-review.googlesource.com/8501 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-20arch-arm, configs: Treat the bootloader rom as cacheable memoryNikos Nikoleris
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-06config: Switch from the print statement to the print function.Gabe Black
Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0 Reviewed-on: https://gem5-review.googlesource.com/8762 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-29config: Embed Device Tree generation in fs.py configGlenn Bergmans
Equips the fs.py config routine with an extra commandline option --generate-dtb that will generate a dtb file automatically before running the simulation. Only works with ARM systems and gives a warning if the simulated system is not of --machine-type VExpress_GEM5_V1. Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5968 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet. Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
Since BaseCPU.createThreads() no longer overrides the BaseCPU.isa parameter, switch_cpus should have the ISA copied. This fixes a fatal error in BaseCPU when restoring from a checkpoint. Change-Id: I4fdcacb76da46bdbe1ce37dcf05c5a6a8a9e5237 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/6241 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05config, mem, hmc: fix HMC test scriptÉder F. Zulian
This patch keeps the logic behind the HMC model implementation untouched. Additional changes: - simple hello world script using HMC (SE simulation) Usage examples: ./build/ARM/gem5.opt configs/example/hmctest.py ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=same ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=mixed ./build/ARM/gem5.opt configs/example/hmc_hello.py ./build/ARM/gem5.opt configs/example/hmc_hello.py --enable-global-monitor --enable-link-monitor Change-Id: I64eb6c9abb45376b6ed72722926acddd50765394 Reviewed-on: https://gem5-review.googlesource.com/6061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-13config: Fix the "script" SysPath functor.Gabe Black
This particular functor looks in the config root, not in the path specified by M5_ROOT like binary and disk. Change-Id: Ib007c36934c65ca9f808e995a2e0c71f0b338788 Reviewed-on: https://gem5-review.googlesource.com/5641 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-31config: Rework the SysPaths functions into functors.Gabe Black
These functions were already being treated as psuedo objects and had properties assigned to them setting what their paths were. That's a bit unusual and made it less obvious what the code was doing, but also forced the "system" function to know what all the possible path searching functions were so that they'd have their "path" property initialized properly in a central location. This change introduces a PathSearcFunc class which encapsulates the mechanisms of the old code and makes it implicitly extensible so that other path searching functions which might look in other directories can be added in other places. Change-Id: I7be28e51481a06ec83997677af99927709b18003 Reviewed-on: https://gem5-review.googlesource.com/5341 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-28config: Discover CPU timing models based on target ISAAndreas Sandberg
The CpuConfig helper currently assumes that all timing models live in the cores.arm package. This ignores the potential mismatch between the target ISA and the ISA assumptions made by the timing models. Instead of unconditionally listing all CPU models in cores.arm, list timing models from cores.generic and cores.${TARGET_ISA}. This ensures that the listed timing models support the ISA that gem5 is targeting. Change-Id: If6235af2118889638f56ac4151003f38edfe9485 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3947 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: Add a high-performance in order timing modelAshkan Tousi
The High-Performance In-order (HPI) CPU timing model is tuned to be representative of a modern in-order ARMv8-A implementation. The HPI core and its supporting simulation scripts, namely starter_se.py and starter_fs.py (under /configs/example/arm/) are part of the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22 Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-07-04config, arm: Don't import timing models for missing CPUsAndreas Sandberg
When importing the cores.arm package, we currently throw an exception if a timing model can't be imported due to a missing dependency (e.g., the required CPU model wasn't included in the build). This is undesirable since it prevents other, working, timing models from being added to the package. Wrap the import_module call in a try-except block and skip timing models that have missing dependencies. Change-Id: I92bab62c989f433a8a4a7bf59207d9d81b3d19e1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3946 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Clean up core timing model discoveryAndreas Sandberg
Instead of hard-coding timing models in CpuConfig.py, use introspection to find them in the cores.arm model package. Change-Id: I6642dc9cbc3f5beeeec748e716c9426c233d51ea Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3944 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Make ex5_*.py independent of old configsAndreas Sandberg
The ex5_LITTLE and ex5_big configs currently depend on Caches.py and O3_ARM_v7a.py. These aren't actual dependencies since all of the params from the caches and the old O3 model are overridden. This changeset updates the ex5 models to derive from the base SimObjects instead. Change-Id: I999e73bb9cc21ad96865c1bc0dd5973faa48ab61 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3942 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-30config: Add missing import of 'fatal' in CpuConfigAndreas Sandberg
Change-Id: I7762d344cb964c3e010135ff928c6ea12538912c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3941 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-30config: Make some MemConfig options optionalAndreas Sandberg
MemConfig currently assumes that all callers include the its full set of options in the command line parser. This is unnecessary and sometimes confusing. Make most of the options optional to avoid having to add all of them to example scripts. Change-Id: I2d73be2454427b00db16716edcfd96a47133c888 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3940 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-19configs, arm: add option to enable security extensionsGedare Bloom
Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3264 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-13config: Warn not fail for ARM systems configured with rubyNikos Nikoleris
Ruby for ARM systems is not fully supported but certain configurations are expected to work. This change removes the more general fail statement and warns or fails depending on the particular configuration. Change-Id: Ic24799aff966ba15858b93482e0f24a8672d9483 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2905 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-18arm, config: added support for ex5 model of big.LITTLEPierre-Yves Péneau
This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-17config: Changes to boot Android NWeiping Liao
necessary kernel command line options in FSConfig.py Change-Id: Id66f640b6beb4efa9c23080c3d2516eda688c72d Reviewed-on: https://gem5-review.googlesource.com/3320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09config: Fix up some configs to not use CPU aliases.Gabe Black
Support for CPU aliases were removed recently. Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f Reviewed-on: https://gem5-review.googlesource.com/3100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-06config: Remove support for CPU aliases.Gabe Black
This was added for backwards compatability, but it adds a decent amount of complexity. The table below shows what CPU class name to use in place of a given alias. +==========+========================================================+ | Alias | CPU class | +==========+========================================================+ | timing | TimingSimpleCPU | | atomic | AtomicSimpleCPU | | minor | MinorCPU | | detailed | DrivO3CPU | | kvm | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch | | trace | TraceCPU | +==========+========================================================+ Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08 Reviewed-on: https://gem5-review.googlesource.com/2940 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05config: Add a default system disk image for SPARC FS.Gabe Black
When the change below removed the hard coded disk name for the SPARC FS configuration, it broke the regression which had not specified a disk name. This change adds a default disk name so that the regression will continue to work like it used to, but preserving the effect of this other change. commit 86a25bbcee88f6e69299867b6264885d738f636e Author: Jakub Jermar <jakub@jermar.eu> Date: Tue Jul 19 09:52:46 2016 -0500 config: Allow SPARC FS image to be specified on the command line Change-Id: Ieb317b2bf573a4f2fc435d34cccd1f246c28d84c Reviewed-on: https://gem5-review.googlesource.com/2645 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-03-01config: exit with fatal() if errorPierre-Yves Péneau
If output redirection is activated, the error message is printed in simout. This change ensure it will be printed in simerr. Change-Id: Ie661ac6b6978bf2e4aaaccdf23134795d764d459 Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2221 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
2017-02-14mem: Update DRAM configuration namesWendy Elsasser
Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH> The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-02-09misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]Christian Menard
The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Restructure the existing sources in preparation of the addition of the * new Master Port. * Refractor names to allow for distinction of the slave and master port. * Replace the Makefile by a SConstruct. Testing Done: The examples provided in util/tlm (now util/tlm/examples/slave_port) still compile and run error free. Reviewed at http://reviews.gem5.org/r/3527/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-12-19sim: Remove redundant buildEnv importAndreas Sandberg
Change-Id: Id6bdbc0c988aa92b96e292cabc913e6b974f14bb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-26dev: Add m5 op to toggle synchronization for dist-gem5.Michael LeBeane
This patch adds the ability for an application to request dist-gem5 to begin/ end synchronization using an m5 op. When toggling on sync, all nodes agree on the next sync point based on the maximum of all nodes' ticks. CPUs are suspended until the sync point to avoid sending network messages until sync has been enabled. Toggling off sync acts like a global execution barrier, where all CPUs are disabled until every node reaches the toggle off point. This avoids tricky situations such as one node hitting a toggle off followed by a toggle on before the other nodes hit the first toggle off.
2016-10-26config: Break out base options for usage with NULL ISAAndreas Hansson
This patch breaks out the most basic configuration options into a set of base options, to allow them to be used also by scripts that do not involve any ISA, and thus no actual CPUs or devices. The patch also fixes a few modules so that they can be imported in a NULL build, and avoid dragging in FSConfig every time Options is imported.
2016-10-15cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClassFernando Endo
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which distinguishes writes to the INT and FP register banks. Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72, where the "latency" of FMADD is 3 if the next instruction is a FMADD and has only the augend to destination dependency, otherwise it's 7 cycles. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-14config: Make configs/common a Python packageAndreas Hansson
Continue along the same line as the recent patch that made the Ruby-related config scripts Python packages and make also the configs/common directory a package. All affected config scripts are updated (hopefully). Note that this change makes it apparent that the current organisation and naming of the config directory and its subdirectories is rather chaotic. We mix scripts that are directly invoked with scripts that merely contain convenience functions. While it is not addressed in this patch we should follow up with a re-organisation of the config structure, and renaming of some of the packages.
2016-10-13ruby: Fix regressions and make Ruby configs Python packagesAndreas Hansson
This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories. As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified.
2016-09-13config: move dist-gem5 options to common configMichael LeBeane
dist-gem5 should not be restricted to FullSystem mode.
2016-08-12mem: Add snoop filter to SystemXBar by defaultAndreas Hansson
This patch changes the default behaviour of the SystemXBar, adding a snoop filter. With the recent updates to the snoop filter allocation behaviour this change no longer causes problems for the regressions without caches. Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-10arm, config: Exit with fatal error if using RubyAndreas Sandberg
Ruby on ARM is currently very experimental. Fail with a fatal error that explains this to make sure users are aware of the limitations (it doesn't actually work yet!). Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-10arm, config: Add initial support for RubyAndreas Sandberg
Add initial support for creating an ARM system with a Ruby-based memory system. This support is currently experimental and limited to the new VExpress_GEM5_V1 platform. Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-07-19config: Allow SPARC FS image to be specified on the command lineJakub Jermar
At the moment the SPARC FS machine configuration comes with a hardcoded value for using the Solaris 10 disk image from the OpenSPARC tarball. The --disk-image option is completely ignored for SPARC. This simple patch modifies the behavior so that --disk-image option is both taken into account and also required. This makes it possible to easily change SPARC FS images without having to modify the configuration files.
2016-07-01mem: different HMC configurationAbdul Mutaal Ahmad
In this new hmc configuration we have used the existing components in gem5 mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different architecture for HMC. Highlights 1- It explores 3 different HMC architectures 2- It creates 4-HMC crossbars and attaches 16 vault controllers with it. This will connect vaults to serial links 3- From the previous version, HMCController with round robin funtionality is being removed and all the serial links are being accessible directly from user ports 4- Latency incorporated by HMCController (in previous version) is being added to SerialLink Committed by Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 04:34:22 +0000