| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-03-21 | ruby: Adds configurable bit selection for numa mapping | Brad Beckmann | |
| 2010-03-21 | ruby: Ruby support for sparse memory | Brad Beckmann | |
| The patch includes direct support for the MI example protocol. | |||
| 2010-03-21 | ruby: fixed how ruby_fs creates phsyical memory | Brad Beckmann | |
| Now ruby_fs creates physical memory of the right size. | |||
| 2010-02-25 | configs: pull out cache configuration code from se.py and fs.py. | Lisa Hsu | |
| Most of these frontend configurations share cache configuration code, pull it out so that changes to caches don't have to require changing multiple config files. | |||
| 2010-01-29 | ruby: Converted Garnet to M5 configuration | Brad Beckmann | |
| 2010-01-29 | ruby: Added a mesh topology | Brad Beckmann | |
| 2010-01-29 | ruby: MOESI_CMP_token updates to use the new config system | Brad Beckmann | |
| 2010-01-29 | ruby: FS support using the new configuration system | Brad Beckmann | |
| 2010-01-29 | ruby: reorganized ruby python configuration | Brad Beckmann | |
| Reorganized ruby python configuration so that protocol and ruby memory system configuration code can be shared by multiple front-end configuration files (i.e. memory tester, full system, and hopefully the regression tester). This code works for memory tester, but have not tested fs mode. | |||
| 2009-12-19 | X86: Record the memory mode when building an X86 system. | Gabe Black | |
| 2009-11-18 | m5: Added option to take a checkpoint at the end of simulation | Brad Beckmann | |
| 2009-11-18 | m5: Moved profile option since Simulation depends on it. | Brad Beckmann | |
| 2009-11-18 | ruby: Support for merging ALPHA_FS and ruby | Brad Beckmann | |
| Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports. | |||
| 2009-09-22 | python: Move more code into m5.util allow SCons to use that code. | Nathan Binkert | |
| Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py | |||
| 2009-09-16 | configs: add maxinsts option on command line | Korey Sewell | |
| -option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of cases then always having to figure out what tick to run your simulation to. | |||
| 2009-05-05 | cpus: fix cpu progress event | Korey Sewell | |
| this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting progress events through repeatEvent flag and also changing the interval of the progress event as well | |||
| 2009-04-26 | X86, Config: Make makeX86System consider the number of CPUs, and clean up ↵ | Gabe Black | |
| interrupt assignment. | |||
| 2008-07-16 | mem: use single BadAddr responder per system. | Steve Reinhardt | |
| Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. | |||
| 2009-04-21 | Minor tweaks for future Ruby compatibility. | Steve Reinhardt | |
| 2009-04-19 | X86: Actually put the PCI INTA entry into the MP tables. | Gabe Black | |
| 2009-04-19 | X86: Make E820 report nice, round (and correct) numbers. | Gabe Black | |
| 2009-04-19 | X86: Automatically make the IO APIC in an N CPU system have id N+1. | Gabe Black | |
| 2009-04-15 | configs: Allow M5_CPU2000 env var to set CPU2K binary path. | Steve Reinhardt | |
| It would be nice to have a more comprehensive mechanism but this is a big improvement over manually editing the script. | |||
| 2009-02-25 | X86: Add IRQ4 to the Intel MP tables. | Gabe Black | |
| 2009-02-10 | Configs: Add support for the InOrder CPU model | Korey Sewell | |
| 2009-02-01 | X86: Find the natural lpj for this configuration. | Gabe Black | |
| 2009-02-01 | X86: Add a root device to the kernel command line. | Gabe Black | |
| 2009-02-01 | X86: Configure the first PCI interrupt. | Gabe Black | |
| 2009-02-01 | X86: Hook in a hard drive image. | Gabe Black | |
| 2009-02-01 | X86: Take out the IDE noprobe kernel arguments. | Gabe Black | |
| 2009-02-01 | X86: Plug in an IDE controller. | Gabe Black | |
| 2009-01-31 | X86: Add some interrupt info to the intel MP tables. | Gabe Black | |
| 2009-01-30 | Errors: Print a URL with a hash of the format string to find more ↵ | Ali Saidi | |
| information about an error. | |||
| 2009-01-25 | X86: Prevent Linux for probing for non-existant IDE controllers. | Gabe Black | |
| 2008-10-11 | X86: Add entries for the IO APIC to the MP table. | Gabe Black | |
| 2008-10-11 | X86: Add an Intel MP table to the simulation. | Gabe Black | |
| 2008-10-11 | X86: Rename the PC device to Pc. | Gabe Black | |
| --HG-- rename : src/dev/x86/PC.py => src/dev/x86/Pc.py | |||
| 2008-10-10 | X86: Turn SMBios structures into simobjects. | Gabe Black | |
| 2008-10-10 | X86: Split makeLinuxX86System into makeLinuxX86System and makeX86System. | Gabe Black | |
| 2008-09-10 | style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵ | Ali Saidi | |
| should configure their editors to not insert tabs | |||
| 2008-06-17 | Rename SimConsole to Terminal since it makes more sense | Nathan Binkert | |
| --HG-- rename : src/dev/SimConsole.py => src/dev/Terminal.py rename : src/dev/simconsole.cc => src/dev/terminal.cc rename : src/dev/simconsole.hh => src/dev/terminal.hh | |||
| 2008-06-12 | X86: Make the e820 table manually or automatically configurable from python. | Gabe Black | |
| 2008-06-12 | X86: Force the kernel to use a certain loops per jiffy instead of ↵ | Gabe Black | |
| calculating it. | |||
| 2008-06-12 | X86: Make the amount of system memory match the hardcoded e820 info. | Gabe Black | |
| 2008-06-12 | X86: Make the regular console use the serial port as well. | Gabe Black | |
| 2008-03-25 | X86: Change the Opteron platform to be the PC platform. | Gabe Black | |
| --HG-- extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37 | |||
| 2008-03-15 | Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint ↵ | Ali Saidi | |
| doesn't exist --HG-- extra : convert_revision : c156c49668815755c4c788f807e8eba32151aa24 | |||
| 2008-02-29 | Error out if -s is used without --caches (instead of saying you must specify a | Lisa Hsu | |
| CPU). --HG-- extra : convert_revision : a3b2bfbe7e037146ac08dd08834bf255da692506 | |||
| 2008-02-29 | Configs: Make sure options don't conflict | Ali Saidi | |
| --HG-- extra : convert_revision : dc9b91cf1d8e33c5e68d7faeb45dbe3e7038d14c | |||
| 2008-02-28 | Configs: Fix some bugs we introduced in the simpoints code | Ali Saidi | |
| --HG-- extra : convert_revision : ef22c11cb3242903a484fc05dc0f96d3e5f9af72 | |||
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