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path: root/configs/common
AgeCommit message (Expand)Author
2013-10-17util: Streamline .apc project convertsion scriptDam Sunwoo
2013-10-17arm, config: Fix a small issue with the dtb file being specifiedAli Saidi
2013-10-09config: correct example ruby scriptsNilay Vaish
2013-09-30x86: Add support for m5ops through a memory mapped interfaceAndreas Sandberg
2013-09-30config: Add a 'kvm' CPU aliasAndreas Sandberg
2013-09-11config: Initialize and check cpt_starttickJoel Hestness
2013-08-26ARM: Fix configuration files for bare-metal binaries.Ali Saidi
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
2013-07-18Configs: Fix up maxtick and maxtimeJoel Hestness
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
2013-06-28configs: rearrange the available options in Options.pyNilay Vaish
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Rename clock option to Ruby clockAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-27config: Add a CPU clock command-line optionAkash Bagdia
2013-06-03config: Add missing CPUs to --restore-with-cpuAndreas Sandberg
2013-05-30mem: More descriptive DRAM config namesAndreas Hansson
2013-05-30mem: Add a LPDDR3-1600 configurationAndreas Hansson
2013-05-30mem: Avoid explicitly zeroing the memory backing storeAndreas Hansson
2013-05-14cpu: remove local/globalHistoryBits params from branch predAnthony Gutierrez
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-04-09Configs: Fix handling of maxtick and take_checkpointsJoel Hestness
2013-03-28x86: create space in bios memory mapNilay Vaish
2013-03-22config: return exit event instead of causeNilay Vaish
2013-02-20config: Fix --prog-interval command line optionAli Saidi
2013-02-15options: add command line option for dtb fileAnthony Gutierrez
2013-02-15config: Remove O3 dependenciesAndreas Sandberg
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-15config: Cleanup CPU configurationAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-02-10config: Don't call sys.exit in interactive mode in run()Andreas Sandberg
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-08config: Fix issue with changeset: a4739b6f799d.Ali Saidi
2013-01-08util: add m5_fail op.LluĂ­s Vilanova
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-11-19config: Fix description of checkpoint option from cycle to tickAndreas Hansson
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson