| Age | Commit message (Collapse) | Author |
|---|
|
The requirement to have an environment variable exported to run a program
is not common, and many new users trip up on it.
Before this commit, M5_PATH was a requirement to run those scripts, or
else simulation would fail with:
IOError: Can't find a path to system files.
After this patch, as long as users indicate all required files with
command line options, M5_PATH is not needed.
This patch changes the M5_PATH semantics slightly to more closely match
PATH and so be more intuitive to users: after this commit, if the
given path contains a slash /, then the path is not searched for inside
M5_PATH, which is exactly how PATH works. Users can then select images
in the CWD with a leading ./ just as done for executables.
This is backwards incompatible if users were already specifying their paths
as ./, but this interface feels saner, because otherwise writing on the CLI
e.g.:
--disk-image path/to/my.disk
would previously fail to find the disk, even if it existed, which is very
counter-intuitive. The following will still fail however:
--disk-image my.disk
which is not ideal, but for now is a comprise between backwards
compatibility of having an M5_PATH and what users expect from CLI
interfaces.
Change-Id: Ic91e1cc20557b35b69490b6dc420e7d324fae1fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23672
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
All ISAs except SPARC can now take multiple disk images by passing
the --disk-image option multiple times.
Before this patch, several ISAs automatically mounted a secondary disk
called "linux-bigswap2.img", which had to be in M5_PATH even if the end
user did not want more than one disk. This was the case for for example
for X86 but not ARM.
This change was done to:
* allow ARM to have a second disk image in fs.py, which was not possible,
and allow other ISAs like X86 and ARM to take any number of disk images
* provide a simpler, more intuitive CLI interface that does not require
magic disk images to be present in M5_PATH to work for ISAs such as X86.
Linux does not need that secondary image to boot correctly, so it is
more friendly to support a minimal setup that requires the least amount
of binaries to boot, and let supply the second image manually only if
they need it.
* make fs.py --disk-image work more similarly across all ISAs
SPARC was left with a single disk only because its setup was a bit more
complex and would require further testing.
Change-Id: I8b6e08ae6daf0a5b6cd1d57d285a9677f01eb7ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23671
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This allows explicitly selecting which bootloader to use.
Before this commit, the bootloader had a fixed basename which
had to be present inside M5_PATH.
Change-Id: I02919207d6f175854017ae7b603d811da63d618e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23670
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Other scripts (like se.py) blindly try to apply the indirect predictor
if one is set. Because this option defaults to something, there's no
way (as far as I know) to purposefully select nothing, and so the
simulator crashes. Users shouldn't have to proactively prevent gem5
from killing itself regardless, so the default was changed to "None".
Change-Id: Ic3382b8065442d6705b1c6a656646598d9d5c322
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23360
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
9p allows the guest Linux kernel to mount a host directory into the guest.
This allows to very easily modify test programs after a run at the end of
boot, without the need to re-insert the changes into a disk image.
It is enabled on both fs.py and fs_bigLITTLE.py with the --vio-9p
option.
Adapted from code originally present on the wiki: http://gem5.org/WA-gem5
As documented in the CLI option help, the current setup requires the guest
to know the full path to the host share, which is annoying, but overcoming
that would require actually parsing a bit of the protocol rather than just
forwarding everything to diod.
Change-Id: Iaeb1ed185dccfa8332fe6657a54e7550f64230eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22831
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Simulation scripts currently need to assign PCI device addresses when
adding new devices. This change moves this responsibility to the
VExpress_GEM5_BASE::attachPciDevice method.
Change-Id: I6d62af8a8f9176d964cc011dd8fb9744154bbb87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22830
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
|
This is the second step towards being able to run dynamically linked
applications when the guest ISA != than host ISA.
Once the guest interpreter is loaded to memory, we are able to redirect
shared object loads through the redirectPath interface.
How do we load the guest interpreter?
The elf file is for example asking for the /lib/ld-linux-aarch64.so
interpreter.
That would point to a valid dynamic linker/loader if guest ISA == host
ISA, but if we are running on X86 we should point to the guest
(aarch64 in the example) toolchain wherever it is installed.
This patch is adding the --interp-dir option to point to the parent
folder of the guest /lib in the host fs.
Change-Id: Id27b97c060008d2e847776a49323d45c8809a27f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23066
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This is the first step towards being able to run dynamically linked
applications when the guest ISA != than host ISA.
(Like running a arm application on x86)
By using the --redirects command line option it is possible to specify
via CLI a set of path redirections to be used in SE mode.
This is needed when running a dynamically linked binary in
SE mode in a guest ISA different than the host. The linker will look
for SOs (e.g. libc.so) in /lib/, but will only find the host libraries.
With this option we can redirect to the guest toolchain/file system.
Usage:
gem5.opt [example script]
--redirects /dir1=/path/to/host/dir1 \
--redirects /dir2=/path/to/host/dir2
Change-Id: I558838be2ad6802891707e9a1cc454786859db15
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23065
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
As it is now, the default behaviour, if chroot is not specified, is to
add a redirect path which is simply mappping "/" in guest to "/" in
host. This patch avoids this unnecessary mapping, and adds a redirect
path to root only if chroot is specified.
Change-Id: Icbe863887330d7071e0005333b408ffc8cad41d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23064
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Typically, a memory controller is assigned an address range of the
form [start, end). This address range might be interleaved and
therefore only a non-continuous subset of the addresses in the address
range is handed by this controller.
Prior to this patch, the DRAM controller was unaware of the
interleaving and as a result the address range could affect the
mapping of addresses to DRAM ranks, rows and columns. This patch
changes the DRAM controller, to transform the input address to a
continuous range of the form [0, size). As a result the DRAM
controller always operates on a dense and continuous address range
regardlesss of the system configuration.
Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Change-Id: I67693e9d79e89f151e30c585ad565deac53c77c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22203
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
When using NULL ISA BaseCPU is undefined, and therefore the
isinstance call generates a NameError.
Change-Id: Ia4582606b775cdb20829966f8e312a333a55b6f3
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21959
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This is because the bus parameter is not used anymore
Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
As far as I can see bootmem is used in Arm systems only.
With
https://gem5-review.googlesource.com/c/public/gem5/+/21604
bootmem has been moved from system to system.realview.
This patch fix things by removing the assumption that the bootmem
SimObject lives under the system.
It is now trying to getattr a reference of the bootmem.
It is the ISA specific system builder's duty to bind the bootmem
reference (_bootmem) to the real bootmem object
Change-Id: I1e7405b5cb186de13c44bfd93fb4c8a1a5447f24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22001
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This patch is pulling the on-chip memory outside of the on_chip_devices
list.
The external interface will be more or less the same: configuration
scripts will still use the attachOnChipIO method; a new kw argument has
been added in order to store mem_ports.
We want to provide to on-chip memory the same mechanism used when
collecting on-chip dma ports. This is needed when using Ruby, since
we need to pass a non None mem_ports to prevent the bootmem to be
wired to the bus.
Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This is an old unused platform. We should support VExpress_GEM5 based
platforms only.
Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Some objects are not compiled when using NULL ISA, and therefore
their object lists cannot exist.
Change-Id: I93ec576229916c892de50bb6c73cd602e18a3654
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21439
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Port PlatformConfig to use the common object list.
Change-Id: If62e596bf1f28b49994da3a2800450d163383755
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20593
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Port MemConfig to use the common object list.
Change-Id: If421c2745ac3431718a5170314045b456fc64a90
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Port HWPConfig to use the common object list.
Change-Id: I86db6b872808f754193dbf5814dd6c951c8f1980
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20591
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Port BPConfig to use the common object list.
Change-Id: I5cbd1c67cf743778bc59b5aa3c3dea5ab397b66d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20590
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Factor out ObjectList functionality from CPUConfig.
Change-Id: I34ca55142e14559e584d38b6cca3aa5c20923521
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20589
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
There are multiple files that reimplement the same functionality
of listing and getting available modules for class instantiation.
Create a base class that can be derived and reduce code duplication.
Change-Id: I96bf47b1ffd10893691b0b95591969b38894dd65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20588
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Commit 224f2d50a9873d054f486d7661d947db76f4cf68 removed all instances
of is_atomic_cpu.
Change-Id: I1101fbdbc16dc5d093ab87d3817308176559a548
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20659
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Commit d207e9ccee411877fdeac80bb68a27900560f50f reworked the tags
to split the replacement policies, however the name of the variable
that contains the replacement policy changed between patch revisions,
which was not updated accordingly in the configs files.
Change-Id: I2072529e2c7d54197c371bcaa323bfd9f34ec3ba
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20548
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
The problem arises since there are some scripts (like NULL dram
regressions) which are making use of MemConfig.py without using
Opions.py so they won't have the new enable-dram-powerdown option
Change-Id: Id9769cce2e8a25b57da76f07eeebd279a6e00440
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19268
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Adding an option to enable DRAM low-power states. The low power
states can have a significant impact on application performance
(sim_ticks) on the order of 2-3x, especially for compute-gpu apps.
The options allows for it to easily be enabled/disabled to compare
performance numbers. The option is disabled by default.
Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This patch updates the FileSystemConfig so it works with more kinds of
config scripts (e.g., the Learning gem5 scripts).
There are 4 main changes:
- Added system as a parameter to the config_filesystem function so the
function can search the system for the number of CPUs instead of relying
on options from Options.py
- Instead of calling redirect_paths everywhere config_filesystem is
used, now it is implicitly called.
- Cleaned up the Ruby scripts a bit to remove redundant calls to
config_filesystem
- Added a config_filesystem call to the Ruby Learning gem5 script
(currently the only Learning gem5 script that requires it).
In the future, I think it would be better to move the config_filesystem
call into simulate.py, probably into the instantiate function. I tried to
use the per-CPU configuration parameters instead of options from
Options.py, but that's not possible until after the SimObject params
have been finalized in instantiate.
Change-Id: Ie6501a7435cfb3ac9d2b45be3722388b34063b1e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18848
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
Change-Id: I5ef5fb7ebc5fc2a4776adc43643c4df27efc341c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18769
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Change-Id: I9a855d36de7d95b7785ff8a897899037cea6a3d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
The NULL ISA does not have some members for the options
class which are referenced by the FileSystemConfig
code.
Create default values for the members so that the
simulation does not fail during the configuration phase.
Change-Id: Ie65bf0e5550c964eae42d1df4c36c2c5bc4ea703
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18748
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
These changes are needed so that the config scripts
can report cache hierarchy information to the faux
filesystem.
This is useful for the ROCm runtime when it reads
psuedofiles from the host filesytem from "/proc".
Change-Id: Iad3e6c088d47c9b93979f584de748367eae8259b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12121
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This change introduces the concept of a faux-filesystem.
The faux-filesystem creates a directory structure in m5out
(or whatever output dir the user specifies) where system calls
may be redirected.
This is useful to avoid non-determinism when reading files
with varying path names (e.g., variations from run-to-run if
the simulation is scheduled on a cluster where paths may change).
Also, this changeset allows circumventing host pseudofiles which
have information specific to the host processor (such as cache
hierarchy or processor information). Bypassing host pseudofiles
can be useful when executing runtimes in the absence of an
operating system kernel since runtimes may try to query standard
files (i.e. /proc or /sys) which are not relevant to an
application executing in syscall emulation mode.
Change-Id: I90821b3b403168b904a662fa98b85def1628621c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
|
|
This patch adds three flag options to set the prefetcher class of the
L1i cache, L1d cache and L2 cache.
Change-Id: I310fcd9c49f9554d98cd565a32bdb96a3e165486
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17709
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The HPI cpu comes with specific cache definitions, but they
are ignored when using this cpu. This patch solves this in the same
way it is done for the O3_ARM_v7a cpu.
Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
One reference was not properly updated when changing to absolute import paths
Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Kernel was being set using a placeholder and then assigned the
correct value. This would generate the following error if the
placeholder file did not exist:
'IOError: Can't find file <placeholder> on path'
This patch follows the same directions of commit
12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default
values, forcing the user to properly configure the kernel.
Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Use absoluate import paths to be Python 3 compatible. This also
imports absolute_import from __future__ to ensure that Python 2.7
behaves the same way as Python 3.
Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Python 2.7 used to return lists for operations such as map and range,
this has changed in Python 3. To make the configs Python 3 compliant,
add explicit conversions from iterators to lists where needed, replace
xrange with range, and fix changes to exec syntax.
This change doesn't fix import paths since that might require us to
restructure the configs slightly.
Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16002
Reviewed-by: Gabe Black <gabeblack@google.com>
|
|
NonCachingCPU is replacing the Atomic+fastmem option.
Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15935
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
Physical memory ranges are now saved in Realview objects as pairs of
addresses (start address and size). This patch is substituting them with
a single AddrRange object.
Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16206
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The option is now enabled if neither --bare-metal nor --dtb-filename are
given.
This is what fs_bigLITTLE.py already did before this patch.
Change-Id: I9179f8c9fa18edbd1e0f1a65ea2c1de0a26b7921
Reviewed-on: https://gem5-review.googlesource.com/c/15899
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Before this commit, there were default magic DTB and kernel filenames
for some platforms.
This was inelegant and error prone, as it refered to out-of-tree files,
and set defaults which users almost always want to customize with
explicit command line options.
One result of this is that a wrong exception could be thrown if --kernel
was given but not --machine-type, since the default machine type
VExpress_EMM had a default kernel, and the code would always search for
the default filename even though --kernel was given:
IOError: Can't find file 'vmlinux.aarch32.ll_20131205.0-gem5' on path.
The defaults existed only for older machine types, and not for the
usually recommended VExpress_GEM5_V1, which suggests that this
deprecation should not affect many users.
Change-Id: Ia49298304f658701ea0800bd79e08db404a655c3
Reviewed-on: https://gem5-review.googlesource.com/c/15898
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7
Reviewed-on: https://gem5-review.googlesource.com/c/14255
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
|
|
Added the parameter "--bp-type" to set the branch predictor type
Added the parameter "--list-bp-types" to list all the available branch
predictor types
Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14015
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The option allows to set SimObject params from the CLI.
The existing config scripts have a large number of options that simply set
a single SimObject parameter, and many still are not exposed.
This commit allows users to pass arbitrary parameters from the command
line to prevent the need for this kind of trivial option.
Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944
Reviewed-on: https://gem5-review.googlesource.com/c/12985
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
This is an old platform, and we haven't had official Linux kernel configs
for it in a while, so we've decided to deprecate it.
Furthermore, trying to use it fails with:
object 'RealViewEB' has no attribute 'pci_host'
and the last commit in the class happened two years ago, which indicates
that no one has been using it.
Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/12471
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform
due to inconsistent UART naming with error message:
AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart'
Consistently name keep all UARTs in the Arm platforms in a vector named
'uart' or as a single device named 'uart'. Update the configuration
scripts to reflect the fact that 'uart' can be a vector.
Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12473
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.
The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.
This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.
Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Both se.py and fs.py need to check if a CPU is a KVM CPU. This is
somewhat involved since CPUs can be disabled at compile time. Enable
better code reuse by moving it to the CpuConfig module.
Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12418
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
