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path: root/configs/dram/sweep.py
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2014-09-03mem: Add utility script to plot DRAM efficiency sweepAndreas Hansson
This patch adds basic functionality to quickly visualise the output from the DRAM efficiency script. There are some unfortunate hacks needed to communicate the needed information from one script to the other, and we fall back on (ab)using the simout to do this. As part of this patch we also trim the efficiency sweep to stop at 512 bytes as this should be sufficient for all forseeable DRAMs.
2014-05-09config: Bump DRAM sweep bus speed to match DDR4 configAndreas Hansson
This patch bumps the bus clock speed such that the interconnect does not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2 GByte/s theoretical max.
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant). As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future. --HG-- rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
2014-03-23config: Add a DRAM efficiency-sweep scriptAndreas Hansson
This patch adds a configuration that simplifies evaluation of DRAM controller configurations by automating a sweep of stride size and bank parallelism. It works in a rather unconventional way, as it needs to print the traffic generator stimuli based on the memory organisation. Hence, it starts by configuring the memory, then it prints a traffic-generator config file, and loads it. The resulting stats have one period per data point, identified by the stride size, and the number of banks being used.