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path: root/configs/example/fs.py
AgeCommit message (Expand)Author
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-02-14MEM: Fix master/slave ports in Ruby and non-regression scriptsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-25MEM: Fix fs.py by specifying the range size rather than endAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-09ARM: Add support for running multiple systemsAli Saidi
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2011-12-01VNC: Add support for capturing frame buffer to file each time it is changed.Chris Emmons
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-03Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
2010-08-23ARM: Add configuration for Linux/Full SystemAli Saidi
2010-02-27Config: Fix fs.py's call to CacheConfig.config_cache.Gabe Black
2010-02-25configs: pull out cache configuration code from se.py and fs.py.Lisa Hsu
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-09-14Add an I/O cache to FS config even if there's just an "L2" cache.Steve Reinhardt
2009-04-26X86, Config: Make makeX86System consider the number of CPUs, and clean up int...Gabe Black
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2009-01-30Errors: Print a URL with a hash of the format string to find more information...Ali Saidi
2008-06-13Scripts: Check for the appropriate build type as soon as possible.Ali Saidi
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
2007-11-15fix MIPS headersKorey Sewell
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-10-08Configuration: Move iocache outside of processors loop so it works for MP sys...Ali Saidi
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
2007-08-08Added fastmem option.Vincentius Robby
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-01Configuration: Update the drive systems kernel as well as the testsys kernel ...Ali Saidi
2007-05-15add an l2 cache option to se example configAli Saidi
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert