gem5 - gem5

Age	Commit message (Expand)	Author
2013-08-19	mem: Change AbstractMemory defaults to match the common case	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2013-06-27	config: Add a CPU clock command-line option	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-04-22	config: Add a mem-type config option to se/fs scripts	Andreas Hansson
2013-04-22	config: Add a KVM VM to systems with KVM CPUs	Andreas Sandberg
2013-02-15	options: add command line option for dtb file	Anthony Gutierrez
2013-01-07	config: Do not use hardcoded physmem in fs script	Andreas Hansson
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-10-26	config: Add a check for fastmem only used with Atomic CPU	Andreas Hansson
2012-10-26	config: Remove unused mem_size in fs.py	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-08-22	Bridge: Remove NACKs in the bridge and unify with packet queue	Andreas Hansson
2012-07-23	Config: Use clock option in se/fs script and pass to switch_cpus	Andreas Hansson
2012-06-07	Config: call to setWorkCountOptions() for all ISAs	Nilay Vaish
2012-06-07	Config: Remove setMipsOptions	Nilay Vaish
2012-06-07	Config: changes to a couple of error msgs	Nilay Vaish
2012-04-16	Config: Add command line options for disk image and memory size	Jayneel Gandhi
2012-04-03	Atomic: Remove the physmem_port and access memory directly	Andreas Hansson
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-03-27	Config: Move setWorkCountOptions() to Simulation.py	Nilay Vaish
2012-03-09	ARM: Fix memory starting at non-zero address and exceeding max mem for a system.	Ali Saidi
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-01	configs: More fixes for the memory system updates	Ali Saidi
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-25	MEM: Fix fs.py by specifying the range size rather than end	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-09	ARM: Add support for running multiple systems	Ali Saidi
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2011-12-01	VNC: Add support for capturing frame buffer to file each time it is changed.	Chris Emmons
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom
2011-02-23	ARM: Clarifies creation of Linux and baremetal ARM systems.	Ali Saidi
2011-02-07	X86, Config: Move the setting of work count options to a separate function.	Gabe Black
2011-02-06	m5: added work completed monitoring support	Brad Beckmann
2011-02-03	Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.	Gabe Black
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-01-19	Time: Add a mechanism to prevent M5 from running faster than real time.	Gabe Black
2010-08-23	ARM: Add configuration for Linux/Full System	Ali Saidi
2010-02-27	Config: Fix fs.py's call to CacheConfig.config_cache.	Gabe Black
2010-02-25	configs: pull out cache configuration code from se.py and fs.py.	Lisa Hsu
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert