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path: root/configs/example/fs.py
AgeCommit message (Expand)Author
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-27config: Add a CPU clock command-line optionAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
2013-04-22config: Add a KVM VM to systems with KVM CPUsAndreas Sandberg
2013-02-15options: add command line option for dtb fileAnthony Gutierrez
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-10-26config: Add a check for fastmem only used with Atomic CPUAndreas Hansson
2012-10-26config: Remove unused mem_size in fs.pyAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-02-14MEM: Fix master/slave ports in Ruby and non-regression scriptsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-25MEM: Fix fs.py by specifying the range size rather than endAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-09ARM: Add support for running multiple systemsAli Saidi
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2011-12-01VNC: Add support for capturing frame buffer to file each time it is changed.Chris Emmons
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-03Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
2010-08-23ARM: Add configuration for Linux/Full SystemAli Saidi
2010-02-27Config: Fix fs.py's call to CacheConfig.config_cache.Gabe Black
2010-02-25configs: pull out cache configuration code from se.py and fs.py.Lisa Hsu
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert