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path: root/configs/example/fs.py
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2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them. The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split). As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch. A bit of tidying up has also been done as part of the simplifications. Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up.
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
This patch changes the se and fs script to use the clock option and not simply set the CPUs clock to 2 GHz. It also makes a minor change to the assignment of the switch_cpus clock to allow different clocks.
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
As status matrix, MIPS fs does not work. Hence, these options are not required. Secondly, the function is setting param values for a CPU class. This seems strange, should probably be done in a different way.
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
Added the options to Options.py for FS mode with backward compatibility. It is good to provide an option to specify the disk image and the memory size from command line since a lot of disk images are created to support different benchmark suites as well as per user needs. Change in program also leads to change in memory requirements. These options provide the interface to provide both disk image and memory size from the command line and gives more flexibility.
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
This patch removes the physmem_port from the Atomic CPU and instead uses the system pointer to access the physmem when using the fastmem option. The system already keeps track of the physmem and the valid memory address ranges, and with this patch we merely make use of that existing functionality. As a result of this change, the overloaded getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
2012-03-28Config: Change the way options are addedNilay Vaish
I am not too happy with the way options are added in files se.py and fs.py currently. This patch moves all the options to the file Options.py, functions from which are called when required.
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
The function is presently defined in FSConfig.py, which does not seem to be the correct place for it.
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
Also clean up how we create boot loader memory a bit.
2012-03-01x86: Fix switching of CPUsNilay Vaish
This patch prevents creation of interrupt controller for cpus that will be switched in later
2012-02-14MEM: Fix master/slave ports in Ruby and non-regression scriptsAndreas Hansson
This patch brings the Ruby and other scripts up to date with the introduction of the master/slave ports.
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-25MEM: Fix fs.py by specifying the range size rather than endAndreas Hansson
This patch fixes the currently broken fs.py by specifying the size of the bridge range rather than the end address. This effectively subtracts one when determining the address range for the IO bridge (from IO bus to membus), and thus avoids the overlapping ranges.
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities. In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.
2012-01-09ARM: Add support for running multiple systemsAli Saidi
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2011-12-01VNC: Add support for capturing frame buffer to file each time it is changed.Chris Emmons
When a change in the frame buffer from the VNC server is detected, the new frame is stored out to the m5out/frames_*/ directory. Specifiy the flag "--frame-capture" when running configs/example/fs.py to enable this behavior. --HG-- extra : rebase_source : d4e08e83f4fa6ff79f3dc9c433fc1f0487e057fc
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
This way things that don't care about work count options and/or aren't called by something that has those command line options set up doesn't have to build a fake object to carry in inert values.
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-03Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
M5 skips over any simulated time where it doesn't have any work to do. When the simulation is active, the time skipped is short and the work done at any point in time is relatively substantial. If the time between events is long and/or the work to do at each event is small, it's possible for simulated time to pass faster than real time. When running a benchmark that can be good because it means the simulation will finish sooner in real time. When interacting with the real world through, for instance, a serial terminal or bridge to a real network, this can be a problem. Human or network response time could be greatly exagerated from the perspective of the simulation and make simulated events happen "too soon" from an external perspective. This change adds the capability to force the simulation to run no faster than real time. It does so by scheduling a periodic event that checks to see if its simulated period is shorter than its real period. If it is, it stalls the simulation until they're equal. This is called time syncing. A future change could add pseudo instructions which turn time syncing on and off from within the simulation. That would allow time syncing to be used for the interactive parts of a session but then turned off when running a benchmark using the m5 utility program inside a script. Time syncing would probably not happen anyway while running a benchmark because there would be plenty of work for M5 to do, but the event overhead could be avoided.
2010-08-23ARM: Add configuration for Linux/Full SystemAli Saidi
2010-02-27Config: Fix fs.py's call to CacheConfig.config_cache.Gabe Black
2010-02-25configs: pull out cache configuration code from se.py and fs.py.Lisa Hsu
Most of these frontend configurations share cache configuration code, pull it out so that changes to caches don't have to require changing multiple config files.
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-14Add an I/O cache to FS config even if there's just an "L2" cache.Steve Reinhardt
2009-04-26X86, Config: Make makeX86System consider the number of CPUs, and clean up ↵Gabe Black
interrupt assignment.
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2009-01-30Errors: Print a URL with a hash of the format string to find more ↵Ali Saidi
information about an error.
2008-06-13Scripts: Check for the appropriate build type as soon as possible.Ali Saidi
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
--HG-- extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
2007-11-15fix MIPS headersKorey Sewell
--HG-- extra : convert_revision : 2870a146a1be0e8c80878090f39c0eaa15d2eb13
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-10-08Configuration: Move iocache outside of processors loop so it works for MP ↵Ali Saidi
systems --HG-- extra : convert_revision : 0ba563555a94eb22a6d4e402388e75e70d3556c2
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
--HG-- extra : convert_revision : 36ed22b50066f54be0e51c3419babc07dd218e10
2007-08-08Added fastmem option.Vincentius Robby
Lets CPU accesses to physical memory bypass Bus. --HG-- extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-01Configuration: Update the drive systems kernel as well as the testsys kernel ↵Ali Saidi
with cmd line option. --HG-- extra : convert_revision : 5dfb0db65452c0b7aa3e2dc2a0209e3f8e23811f
2007-05-15add an l2 cache option to se example configAli Saidi
configs/common/Options.py: configs/example/fs.py: move l2 cache option to Options.py --HG-- extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3