gem5 - gem5

Age	Commit message (Expand)	Author
2012-04-03	Atomic: Remove the physmem_port and access memory directly	Andreas Hansson
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-03-27	Config: Move setWorkCountOptions() to Simulation.py	Nilay Vaish
2012-03-09	ARM: Fix memory starting at non-zero address and exceeding max mem for a system.	Ali Saidi
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-01	configs: More fixes for the memory system updates	Ali Saidi
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-25	MEM: Fix fs.py by specifying the range size rather than end	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-09	ARM: Add support for running multiple systems	Ali Saidi
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2011-12-01	VNC: Add support for capturing frame buffer to file each time it is changed.	Chris Emmons
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom
2011-02-23	ARM: Clarifies creation of Linux and baremetal ARM systems.	Ali Saidi
2011-02-07	X86, Config: Move the setting of work count options to a separate function.	Gabe Black
2011-02-06	m5: added work completed monitoring support	Brad Beckmann
2011-02-03	Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.	Gabe Black
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-01-19	Time: Add a mechanism to prevent M5 from running faster than real time.	Gabe Black
2010-08-23	ARM: Add configuration for Linux/Full System	Ali Saidi
2010-02-27	Config: Fix fs.py's call to CacheConfig.config_cache.	Gabe Black
2010-02-25	configs: pull out cache configuration code from se.py and fs.py.	Lisa Hsu
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2009-09-14	Add an I/O cache to FS config even if there's just an "L2" cache.	Steve Reinhardt
2009-04-26	X86, Config: Make makeX86System consider the number of CPUs, and clean up int...	Gabe Black
2008-07-16	mem: use single BadAddr responder per system.	Steve Reinhardt
2009-01-30	Errors: Print a URL with a hash of the format string to find more information...	Ali Saidi
2008-06-13	Scripts: Check for the appropriate build type as soon as possible.	Ali Saidi
2007-12-01	X86: Move startup code to the system object to initialize a Linux system.	Gabe Black
2007-11-15	fix MIPS headers	Korey Sewell
2007-11-13	Add in files from merge-bare-iron, get them compiling in FS and SE mode	Korey Sewell
2007-10-08	Configuration: Move iocache outside of processors loop so it works for MP sys...	Ali Saidi
2007-10-07	X86: Adjust the config scripts for x86 fs.	Gabe Black
2007-08-08	Added fastmem option.	Vincentius Robby
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-01	Configuration: Update the drive systems kernel as well as the testsys kernel ...	Ali Saidi
2007-05-15	add an l2 cache option to se example config	Ali Saidi
2007-03-06	Move all of the parameters of the Root SimObject so they are	Nathan Binkert
2007-01-03	Merge zizzer:/bk/newmem	Gabe Black
2006-12-22	Add options for setting the kernel to run and the	Nathan Binkert
2006-12-04	automatically build sparc system or alpha system.	Lisa Hsu
2006-11-15	Add L2 cache option to fs.py --l2cache	Ron Dreslinski
2006-11-09	Clean up config scripts to not have to worry about attaching a cache only to ...	Kevin Lim
2006-11-01	factor some more commone code and enable going from checkpoint into arbitrary...	Lisa Hsu