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2017-02-14mem: Update DRAM configuration namesWendy Elsasser
Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH> The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-12-05config: Add an option to generate a random topology in memcheckNikos Nikoleris
This change adds the option to use the memcheck with random memory hierarchies at the moment limited to a maximum depth of 3 allowing testing with uncommon topologies. Change-Id: Id2c2fe82a8175d9a67eb4cd7f3d2e2720a809b60 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-12-05config: Add whole line accesses to improve memchecker's coverageNikos Nikoleris
Change-Id: Ie1a047139e350ce7400f3a20be644eaff1e21428 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-04-21config: Add missing point of coherency to memcheck scriptAndreas Hansson
Bring in line with changes to the XBar class.
2015-08-21mem: Add explicit Cache subclass and make BaseCache abstractAndreas Hansson
Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. --HG-- rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
This patch takes the final step in removing the is_top_level parameter from the cache. With the recent changes to read requests and write invalidations, the parameter is no longer needed, and consequently removed. This also means that asymmetric cache hierarchies are now fully supported (and we are actually using them already with L1 caches, but no table-walker caches, connected to a shared L2).
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
2015-02-16config: Add memcheck stress testAndreas Hansson
This is a rather unfortunate copy of the memtest.py example script, that actually stresses the system with true sharing as opposed to the false sharing of the MemTest. To do so it uses TrafficGen instances to generate the reads/writes, and MemCheckerMonitor combined with the MemChecker to check the validity of the read/written values. As a bonus, this script also enables the addition of prefetchers, and the traffic is created to have a mix of random addresses and linear strides. We use the TaggedPrefetcher since the packets do not have a request with a PC. At the moment the code is almost identical to the memtest.py script, and no effort has been made to factor out the construction of the tree. The challenge is that the instantiation and connection of the testers and monitors is done as part of the tree building.