index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
configs
/
example
/
memtest.py
Age
Commit message (
Expand
)
Author
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
2012-02-14
MEM: Fix residual bus ports and make them master/slave
Andreas Hansson
2012-01-28
SE/FS: Make SE vs. FS mode a runtime parameter.
Gabe Black
2010-08-25
memtest: scale associativity and mshrs according to config
Steve Reinhardt
2010-08-17
sim: make Python Root object a singleton
Steve Reinhardt
2009-09-22
python: Move more code into m5.util allow SCons to use that code.
Nathan Binkert
2007-07-15
Fix up a bunch of multilevel coherence issues.
Steve Reinhardt
2007-07-15
Fix problem with unset max_loads in memtest.
Steve Reinhardt
2007-07-15
Punt on old -n/-c memtest args.
Steve Reinhardt
2007-07-15
Add --force-bus option to memtest.py.
Steve Reinhardt
2007-07-14
New tree-based algorithm for creating more complex cache hierarchies.
Steve Reinhardt
2007-06-27
Get rid of coherence protocol object.
Steve Reinhardt
2007-06-21
Getting closer...
Steve Reinhardt
2007-06-17
More major reorg of cache. Seems to work for atomic mode now,
Steve Reinhardt
2007-05-22
memtest.py:
Steve Reinhardt
2007-05-19
PhysicalMemory has vector of uniform ports instead of one special one.
Steve Reinhardt
2006-11-12
Update for maxtick in splash2/memtest configs
Ron Dreslinski
2006-10-20
Give physical memory some latency to stress the system
Ron Dreslinski
2006-10-20
Add a config file in the example with the memtester and some parser options.
Ron Dreslinski