gem5 - gem5

Age	Commit message (Expand)	Author
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-11-06	ruby: single physical memory in fs mode	Nilay Vaish
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-09-20	cpu: use probes infrastructure to do simpoint profiling	Dam Sunwoo
2014-09-01	ruby: Fixes clock domains in configuration files	Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-04-01	configs: use SimpleMemory when using ruby in se mode	Nilay Vaish
2014-03-20	config: ruby: rename _cpu_ruby_ports to _cpu_ports	Nilay Vaish
2014-03-20	config: remove ruby_fs.py	Nilay Vaish
2014-03-20	ruby: no piobus in se mode	Nilay Vaish
2014-02-24	ruby: correct errors in changeset 4eec7bdde5b0	Nilay Vaish
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-10-07	config: set cwd for processes in se.py	Nilay Vaish
2013-08-19	config: Command line support for multi-channel memory	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-07-18	config: Update script to set cache line size on system	Andreas Hansson
2013-06-28	configs: rearrange the available options in Options.py	Nilay Vaish
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2013-06-27	config: Add a CPU clock command-line option	Akash Bagdia
2013-06-13	config: Do not instantiate membus when using ruby	Nilay Vaish
2013-04-22	config: Add a mem-type config option to se/fs scripts	Andreas Hansson
2013-04-22	cpu: generate SimPoint basic block vector profiles	Dam Sunwoo
2013-03-06	ruby: remove the functional copy of memory in se mode	Nilay Vaish
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-10-26	config: Add a check for fastmem only used with Atomic CPU	Andreas Hansson
2012-09-28	Configs: SE script fix for Alpha and Ruby simulations	Malek Musleh
2012-09-12	se.py Ruby: Connect TLB walker ports	Joel Hestness
2012-09-11	se.py: removes error in passing options to a binary	Nilay Vaish
2012-09-09	se.py: support specifying multiple programs via command line	Nilay Vaish
2012-07-23	Config: Use clock option in se/fs script and pass to switch_cpus	Andreas Hansson
2012-07-10	ruby: changes how Topologies are created	Brad Beckmann
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-16	Config: Fix a typo in the se.py script for setting fastmem	Andreas Hansson
2012-04-17	SE Config: Changed se.py to support multithreaded mode	Jayneel Gandhi
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-03	Atomic: Remove the physmem_port and access memory directly	Andreas Hansson
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-03-11	se.py: Changes to ruby portion due to SE/FS merge	Nilay Vaish
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-01	Config: make option ruby available always	Nilay Vaish
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	Ruby: Connect system port in Ruby network test	Andreas Hansson
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-05	Config: Add an option of type 'choice' for cpu type	Nilay Vaish
2011-08-02	Scons: Drop RUBY as compile time option.	Nilay Vaish