index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
configs
/
example
/
se.py
Age
Commit message (
Expand
)
Author
2007-05-15
add an l2 cache option to se example config
Ali Saidi
2006-11-09
Clean up config scripts to not have to worry about attaching a cache only to ...
Kevin Lim
2006-11-01
factor some more commone code and enable going from checkpoint into arbitrary...
Lisa Hsu
2006-10-31
Fix up configs.
Kevin Lim
2006-10-31
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-10-31
Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...
Kevin Lim
2006-10-30
se.py, fs.py:
Lisa Hsu
2006-10-30
Use some python os.path stuff to make it more flexible where we can execute t...
Kevin Lim
2006-10-27
factor out common run code from se.py and fs.py.
Lisa Hsu
2006-10-23
warmup of 1B cpu cycles.
Lisa Hsu
2006-10-23
make a lot of the same changes as to fs.py for checkpointing.
Lisa Hsu
2006-10-09
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-10-08
Set cpu_id params (required by ll/sc code now).
Steve Reinhardt
2006-10-08
Clean up configs.
Kevin Lim
2006-08-29
Add missing cpu mem param to example/se.py.
Steve Reinhardt
2006-08-16
Finish test clean-up & reorg.
Steve Reinhardt