summaryrefslogtreecommitdiff
path: root/configs/example/se.py
AgeCommit message (Expand)Author
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
2017-02-14sim, kvm: make KvmVM a System parameterCurtis Dunham
2016-10-14config: Make configs/common a Python packageAndreas Hansson
2016-10-13ruby: Fix regressions and make Ruby configs Python packagesAndreas Hansson
2016-10-06config: add a separate config file for the network.Tushar Krishna
2015-12-07config: Enable elastic trace capture and replay in se/fsRadhika Jagtap
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-09-30config,cpu: Add SMT support to Atomic and Timing CPUsMitch Hayenga
2015-09-06config: allow ruby to be used with Minor CPUNilay Vaish
2015-04-23config: enable setting SE-mode environment variables from filebpotter
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-01-20scons: Do not build the InOrderCPUAndreas Hansson
2014-11-23config, kvm: Enabling KvmCPU in SE modeAlexandru Dutu
2014-11-18configs: small fix to ruby portion of fs.py and se.pyNilay Vaish
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20cpu: use probes infrastructure to do simpoint profilingDam Sunwoo
2014-09-01ruby: Fixes clock domains in configuration filesEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-04-01configs: use SimpleMemory when using ruby in se modeNilay Vaish
2014-03-20config: ruby: rename _cpu_ruby_ports to _cpu_portsNilay Vaish
2014-03-20config: remove ruby_fs.pyNilay Vaish
2014-03-20ruby: no piobus in se modeNilay Vaish
2014-02-24ruby: correct errors in changeset 4eec7bdde5b0Nilay Vaish
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-10-07config: set cwd for processes in se.pyNilay Vaish
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-07-18config: Update script to set cache line size on systemAndreas Hansson
2013-06-28configs: rearrange the available options in Options.pyNilay Vaish
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-27config: Add a CPU clock command-line optionAkash Bagdia
2013-06-13config: Do not instantiate membus when using rubyNilay Vaish
2013-04-22config: Add a mem-type config option to se/fs scriptsAndreas Hansson
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-10-26config: Add a check for fastmem only used with Atomic CPUAndreas Hansson
2012-09-28Configs: SE script fix for Alpha and Ruby simulationsMalek Musleh
2012-09-12se.py Ruby: Connect TLB walker portsJoel Hestness
2012-09-11se.py: removes error in passing options to a binaryNilay Vaish
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-16Config: Fix a typo in the se.py script for setting fastmemAndreas Hansson
2012-04-17SE Config: Changed se.py to support multithreaded modeJayneel Gandhi
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson