gem5 - gem5

Age	Commit message (Expand)	Author
2008-07-23	process: separate stderr from stdout	Michael Adler
2008-06-13	Scripts: Check for the appropriate build type as soon as possible.	Ali Saidi
2008-02-28	Configs: Fix some bugs we introduced in the simpoints code	Ali Saidi
2007-12-01	X86: Move startup code to the system object to initialize a Linux system.	Gabe Black
2007-11-15	fix MIPS headers	Korey Sewell
2007-11-13	Add in files from merge-bare-iron, get them compiling in FS and SE mode	Korey Sewell
2007-10-08	Configuration: Move iocache outside of processors loop so it works for MP sys...	Ali Saidi
2007-10-07	X86: Adjust the config scripts for x86 fs.	Gabe Black
2007-09-05	Configuration: Fix example script to only create one L2 if --l2cache and -nX ...	Ali Saidi
2007-08-08	Added fastmem option.	Vincentius Robby
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-03	merge from head	Steve Reinhardt
2007-08-02	merge, no manual changes	Ali Saidi
2007-08-01	Fix how the "cmd" parameter is set in se.py and remove hack in x86 process in...	Gabe Black
2007-08-01	Configuration: Update the drive systems kernel as well as the testsys kernel ...	Ali Saidi
2007-07-15	Fix up a bunch of multilevel coherence issues.	Steve Reinhardt
2007-07-15	Fix problem with unset max_loads in memtest.	Steve Reinhardt
2007-07-15	Punt on old -n/-c memtest args.	Steve Reinhardt
2007-07-15	Add --force-bus option to memtest.py.	Steve Reinhardt
2007-07-14	New tree-based algorithm for creating more complex cache hierarchies.	Steve Reinhardt
2007-06-27	Get rid of coherence protocol object.	Steve Reinhardt
2007-06-21	Getting closer...	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-06-09	More realistic parameters	Nathan Binkert
2007-05-22	memtest.py:	Steve Reinhardt
2007-05-19	PhysicalMemory has vector of uniform ports instead of one special one.	Steve Reinhardt
2007-05-15	add an l2 cache option to se example config	Ali Saidi
2007-03-06	Move all of the parameters of the Root SimObject so they are	Nathan Binkert
2007-01-03	Merge zizzer:/bk/newmem	Gabe Black
2006-12-22	Add options for setting the kernel to run and the	Nathan Binkert
2006-12-04	automatically build sparc system or alpha system.	Lisa Hsu
2006-11-15	Add L2 cache option to fs.py --l2cache	Ron Dreslinski
2006-11-12	Merge ktlim@zamp:./local/clean/tmp/test-regress	Kevin Lim
2006-11-12	Update for maxtick in splash2/memtest configs	Ron Dreslinski
2006-11-09	Clean up config scripts to not have to worry about attaching a cache only to ...	Kevin Lim
2006-11-01	factor some more commone code and enable going from checkpoint into arbitrary...	Lisa Hsu
2006-10-31	Fix up configs.	Kevin Lim
2006-10-31	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-10-31	Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...	Kevin Lim
2006-10-30	se.py, fs.py:	Lisa Hsu
2006-10-30	Use some python os.path stuff to make it more flexible where we can execute t...	Kevin Lim
2006-10-27	factor out common run code from se.py and fs.py.	Lisa Hsu
2006-10-24	Fix fs.py. Lisa did you test this? Is there some wierd python version thing?	Ali Saidi
2006-10-23	warmup of 1B cpu cycles.	Lisa Hsu
2006-10-23	Merge zizzer:/bk/newmem	Lisa Hsu
2006-10-23	make a lot of the same changes as to fs.py for checkpointing.	Lisa Hsu
2006-10-23	changes regarding fs.py	Lisa Hsu
2006-10-20	Give physical memory some latency to stress the system	Ron Dreslinski
2006-10-20	Add a config file in the example with the memtester and some parser options.	Ron Dreslinski
2006-10-19	First cut at LL/SC support in caches (atomic mode only).	Steve Reinhardt