summaryrefslogtreecommitdiff
path: root/configs/example
AgeCommit message (Expand)Author
2009-04-26X86, Config: Make makeX86System consider the number of CPUs, and clean up int...Gabe Black
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
2009-01-30Errors: Print a URL with a hash of the format string to find more information...Ali Saidi
2008-07-23process: separate stderr from stdoutMichael Adler
2008-06-13Scripts: Check for the appropriate build type as soon as possible.Ali Saidi
2008-02-28Configs: Fix some bugs we introduced in the simpoints codeAli Saidi
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
2007-11-15fix MIPS headersKorey Sewell
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-10-08Configuration: Move iocache outside of processors loop so it works for MP sys...Ali Saidi
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
2007-09-05Configuration: Fix example script to only create one L2 if --l2cache and -nX ...Ali Saidi
2007-08-08Added fastmem option.Vincentius Robby
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-03merge from headSteve Reinhardt
2007-08-02merge, no manual changesAli Saidi
2007-08-01Fix how the "cmd" parameter is set in se.py and remove hack in x86 process in...Gabe Black
2007-08-01Configuration: Update the drive systems kernel as well as the testsys kernel ...Ali Saidi
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
2007-07-15Fix problem with unset max_loads in memtest.Steve Reinhardt
2007-07-15Punt on old -n/-c memtest args.Steve Reinhardt
2007-07-15Add --force-bus option to memtest.py.Steve Reinhardt
2007-07-14New tree-based algorithm for creating more complex cache hierarchies.Steve Reinhardt
2007-06-27Get rid of coherence protocol object.Steve Reinhardt
2007-06-21Getting closer...Steve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-06-09More realistic parametersNathan Binkert
2007-05-22memtest.py:Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-05-15add an l2 cache option to se example configAli Saidi
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-01-03Merge zizzer:/bk/newmemGabe Black
2006-12-22Add options for setting the kernel to run and theNathan Binkert
2006-12-04automatically build sparc system or alpha system.Lisa Hsu
2006-11-15Add L2 cache option to fs.py --l2cacheRon Dreslinski
2006-11-12Merge ktlim@zamp:./local/clean/tmp/test-regressKevin Lim
2006-11-12Update for maxtick in splash2/memtest configsRon Dreslinski
2006-11-09Clean up config scripts to not have to worry about attaching a cache only to ...Kevin Lim
2006-11-01factor some more commone code and enable going from checkpoint into arbitrary...Lisa Hsu
2006-10-31Fix up configs.Kevin Lim
2006-10-31Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-30se.py, fs.py:Lisa Hsu
2006-10-30Use some python os.path stuff to make it more flexible where we can execute t...Kevin Lim
2006-10-27factor out common run code from se.py and fs.py.Lisa Hsu
2006-10-24Fix fs.py. Lisa did you test this? Is there some wierd python version thing?Ali Saidi
2006-10-23warmup of 1B cpu cycles.Lisa Hsu
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
2006-10-23make a lot of the same changes as to fs.py for checkpointing.Lisa Hsu
2006-10-23changes regarding fs.pyLisa Hsu
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 17:02:37 +0000