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AgeCommit message (Expand)Author
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-02-15options: add command line option for dtb fileAnthony Gutierrez
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-12-11ruby: modify the directed tester to read/write streamsNilay Vaish
2012-10-26config: Add a check for fastmem only used with Atomic CPUAndreas Hansson
2012-10-26config: Remove unused mem_size in fs.pyAndreas Hansson
2012-10-15ruby: improved support for functional accessesNilay Vaish
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-28Configs: SE script fix for Alpha and Ruby simulationsMalek Musleh
2012-09-27Configs: Fix memtest cache latency to match new parametersAndreas Hansson
2012-09-27Configs: Fix memtest.py by moving the system portAndreas Hansson
2012-09-12se.py Ruby: Connect TLB walker portsJoel Hestness
2012-09-11se.py: removes error in passing options to a binaryNilay Vaish
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-16Config: Fix a typo in the se.py script for setting fastmemAndreas Hansson
2012-04-17SE Config: Changed se.py to support multithreaded modeJayneel Gandhi
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-04-05Ruby: Fix the example configurations option parsingAndreas Hansson
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-16ruby_fs.py: Add call to createInterruptController()Nilay Vaish
2012-03-11se.py: Changes to ruby portion due to SE/FS mergeNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-03-01Config: make option ruby available alwaysNilay Vaish
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson
2012-02-14MEM: Fix master/slave ports in Ruby and non-regression scriptsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-30Merge with main repository.Gabe Black
2012-01-30Ruby: Connect system port in Ruby network testAndreas Hansson
2012-01-29Yet another merge with the main repository.Gabe Black