gem5 - gem5

Age	Commit message (Expand)	Author
2012-07-23	Config: Use clock option in se/fs script and pass to switch_cpus	Andreas Hansson
2012-07-12	Mem: Make SimpleMemory single ported	Andreas Hansson
2012-07-10	ruby: remove the cpu assumptions for the random tester	Brad Beckmann
2012-07-10	ruby: changes how Topologies are created	Brad Beckmann
2012-06-07	Config: call to setWorkCountOptions() for all ISAs	Nilay Vaish
2012-06-07	Config: Remove setMipsOptions	Nilay Vaish
2012-06-07	Config: changes to a couple of error msgs	Nilay Vaish
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-05-16	Config: Fix a typo in the se.py script for setting fastmem	Andreas Hansson
2012-04-17	SE Config: Changed se.py to support multithreaded mode	Jayneel Gandhi
2012-04-16	Config: Add command line options for disk image and memory size	Jayneel Gandhi
2012-04-06	rubytest: seperated read and write ports.	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-04-05	Ruby: Fix the example configurations option parsing	Andreas Hansson
2012-04-03	Atomic: Remove the physmem_port and access memory directly	Andreas Hansson
2012-03-28	Config: Change the way options are added	Nilay Vaish
2012-03-27	Config: Move setWorkCountOptions() to Simulation.py	Nilay Vaish
2012-03-16	ruby_fs.py: Add call to createInterruptController()	Nilay Vaish
2012-03-11	se.py: Changes to ruby portion due to SE/FS merge	Nilay Vaish
2012-03-09	ARM: Fix memory starting at non-zero address and exceeding max mem for a system.	Ali Saidi
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-03-01	Config: make option ruby available always	Nilay Vaish
2012-02-14	MEM: Fix residual bus ports and make them master/slave	Andreas Hansson
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-01	configs: More fixes for the memory system updates	Ali Saidi
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	Ruby: Connect system port in Ruby network test	Andreas Hansson
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-28	Config: Enable O3 CPU and Ruby in FS mode	Nilay Vaish
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-25	MEM: Fix fs.py by specifying the range size rather than end	Andreas Hansson
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-09	ARM: Add support for running multiple systems	Ali Saidi
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-05	Config: Add an option of type 'choice' for cpu type	Nilay Vaish
2011-12-01	VNC: Add support for capturing frame buffer to file each time it is changed.	Chris Emmons
2011-10-29	Ruby FS: Add the options for kernel and simulation script	Nilay Vaish
2011-08-02	Scons: Drop RUBY as compile time option.	Nilay Vaish
2011-07-11	se.py: Fixes the way ruby's options are added	Nilay Vaish
2011-06-30	config: removed unnecessary slashes	Brad Beckmann
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom