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2009-11-18m5: improvements to the ruby_fs.py fileBrad Beckmann
2009-11-18ruby: included ruby config parameter ports per coreBrad Beckmann
Slightly improved the major hack need to correctly assign the number of ports per core. CPUs have two ports: icache + dcache. MemTester has one port.
2009-11-18ruby: Support for merging ALPHA_FS and rubyBrad Beckmann
Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports.
2009-11-18ruby: Ruby memtest python script.Brad Beckmann
2009-10-16removed libruby file reference from ruby_se.pyBrad Beckmann
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-16inorder-configs: update se.pyKorey Sewell
fix bug with 'numThreads=len(workloads)' which was counting characters of command-line not counting threads as intended. Update numThreads for inorder/o3 cases and default to 1 for all other cases.
2009-09-14Add an I/O cache to FS config even if there's just an "L2" cache.Steve Reinhardt
2009-07-26se-configs: edit se.py to account for non-O3CPU workloadsKorey Sewell
2009-07-25o3-smt: enforce numThreads parameter for SMT SE modeKorey Sewell
2009-05-11ruby: Working M5 interface and updated Ruby interface.Daniel Sanchez
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu> RubyMemory is now both a driver for Ruby and a port for M5. Changed makeRequest/hitCallback interface. Brought packets (superficially) into the sequencer. Modified tester infrastructure to be packet based. and Ruby can be used together through the example ruby_se.py script. SPARC parallel applications work, and the timing *seems* right from combined M5/Ruby debug traces. To run, % build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-04-26X86, Config: Make makeX86System consider the number of CPUs, and clean up ↵Gabe Black
interrupt assignment.
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2009-01-30Errors: Print a URL with a hash of the format string to find more ↵Ali Saidi
information about an error.
2008-07-23process: separate stderr from stdoutMichael Adler
- Add the option of redirecting stderr to a file. With the old behaviour, stderr would follow stdout if stdout was to a file, but stderr went to the host stderr if stdout went to the host stdout. The new default maintains stdout and stderr going to the host. Now the two can specify different files, but they will share a file descriptor if the name of the files is the same. - Add --output and --errout options to se.py to go with --input.
2008-06-13Scripts: Check for the appropriate build type as soon as possible.Ali Saidi
2008-02-28Configs: Fix some bugs we introduced in the simpoints codeAli Saidi
--HG-- extra : convert_revision : ef22c11cb3242903a484fc05dc0f96d3e5f9af72
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
--HG-- extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
2007-11-15fix MIPS headersKorey Sewell
--HG-- extra : convert_revision : 2870a146a1be0e8c80878090f39c0eaa15d2eb13
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-10-08Configuration: Move iocache outside of processors loop so it works for MP ↵Ali Saidi
systems --HG-- extra : convert_revision : 0ba563555a94eb22a6d4e402388e75e70d3556c2
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
--HG-- extra : convert_revision : 36ed22b50066f54be0e51c3419babc07dd218e10
2007-09-05Configuration: Fix example script to only create one L2 if --l2cache and -nX ↵Ali Saidi
are given as parameters. Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de] --HG-- extra : convert_revision : 1dfc548d2bc33d622d829bbf385f4bf9700711cd
2007-08-08Added fastmem option.Vincentius Robby
Lets CPU accesses to physical memory bypass Bus. --HG-- extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-03merge from headSteve Reinhardt
--HG-- extra : convert_revision : 21f7afe2719c00744c0981212c1ee6e442238e01
2007-08-02merge, no manual changesAli Saidi
--HG-- extra : convert_revision : 8504bddf1f73a4186cebc03c3e52e42ea38361fc
2007-08-01Fix how the "cmd" parameter is set in se.py and remove hack in x86 process ↵Gabe Black
initialization code. --HG-- extra : convert_revision : 1fc741eea956ebfa4cef488eef4333d1f50617a6
2007-08-01Configuration: Update the drive systems kernel as well as the testsys kernel ↵Ali Saidi
with cmd line option. --HG-- extra : convert_revision : 5dfb0db65452c0b7aa3e2dc2a0209e3f8e23811f
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
Atomic mode seems to work. Timing is closer but not there yet. --HG-- extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15Fix problem with unset max_loads in memtest.Steve Reinhardt
Also make default 0, and make that mean run forever. --HG-- extra : convert_revision : 3e60a52b1c5e334a9ef3d744cf7ee1d851ba4aa9
2007-07-15Punt on old -n/-c memtest args.Steve Reinhardt
Also added comments to document treespec format. --HG-- extra : convert_revision : fa9e8f66b68b96a4efca8a7fe6e7c37367382d9d
2007-07-15Add --force-bus option to memtest.py.Steve Reinhardt
--HG-- extra : convert_revision : 101735cca426903704ff2edaff051fa7c5bfc46c
2007-07-14New tree-based algorithm for creating more complex cache hierarchies.Steve Reinhardt
--HG-- extra : convert_revision : de8dd4ef5dae0f3e084461e8ef7c549653e61d3f
2007-06-27Get rid of coherence protocol object.Steve Reinhardt
--HG-- extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
2007-06-21Getting closer...Steve Reinhardt
configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. --HG-- extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-09More realistic parametersNathan Binkert
--HG-- extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
2007-05-22memtest.py:Steve Reinhardt
Make clocks more reasonable. Fix bug in sense of options.timing flag. configs/example/memtest.py: Fix bug in sense of options.timing flag. configs/example/memtest.py: Make clocks more reasonable. --HG-- extra : convert_revision : 3715697988c56e92a4da129b42026d0623f5e85e
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-15add an l2 cache option to se example configAli Saidi
configs/common/Options.py: configs/example/fs.py: move l2 cache option to Options.py --HG-- extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-01-03Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2006-12-22Add options for setting the kernel to run and theNathan Binkert
script to run --HG-- extra : convert_revision : 32ad8e08ca74edf042d8606ca4876cbe1193e932
2006-12-04automatically build sparc system or alpha system.Lisa Hsu
configs/example/fs.py: make it an automatic system build for alpha vs. sparc. --HG-- extra : convert_revision : 4c217cf9309c6209be7f80e358f6640857a785e8
2006-11-15Add L2 cache option to fs.py --l2cacheRon Dreslinski
--HG-- extra : convert_revision : 5bdd1129c3b23e91d441e7b83f6a824ef7740fab
2006-11-12Merge ktlim@zamp:./local/clean/tmp/test-regressKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
2006-11-12Update for maxtick in splash2/memtest configsRon Dreslinski
configs/example/memtest.py: configs/splash2/run.py: Update for maxtick --HG-- extra : convert_revision : 94106625be1ebc2b614db16720a4861e47222c0b
2006-11-09Clean up config scripts to not have to worry about attaching a cache only to ↵Kevin Lim
the TimingCPU. Now the Atomic CPU works with caches. configs/common/Simulation.py: Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU. However the O3CPU must always use caches, so a check for that must still exist. Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU. configs/example/fs.py: configs/example/se.py: Atomic CPU now handles caches. --HG-- extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
2006-11-01factor some more commone code and enable going from checkpoint into ↵Lisa Hsu
arbitrary CPU with or without caches. configs/common/Simulation.py: enable going from checkpoint into arbitrary CPU with or without caches. --HG-- extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
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