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2017-08-03configs, arm: Fix incorrect use of mem_range in bL exampleAndreas Sandberg
The change "config: Change mem_range attribute naming in ARM SimpleSystem" modified the SimpleSystem class to be compatible with the MemConfig utility script. While doing so, the way we report the memory ranges supported by the system changed, which broke the bL example configration. This changeset introduces the necessary changes to make the script work again. Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-03arm, config: Fix CPU names in ARM example configsAndreas Sandberg
The ARM example configs used to rely on CPU aliases for the AtomicSimpleCPU and KVM when configuring clusters. This broken when support for CPU aliases was removed ('config: Remove support for CPU aliases.'). This change updates the config scripts to use the full class names instead. Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4360 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
Old ARM systems used to pass the machine type in the ATAGS list passed to the kernel. This has been largely deprecated by the introduction of device trees. Switch to the DTOnly machine type by default in gem5 since all new platforms and kernel will require this behavior. Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4260 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: SE configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4203 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: FS configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4202 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config: Change mem_range attribute naming in ARM SimpleSystemGabor Dozsa
MemConfig.config() expects memory ranges to be defined in a particular way. This patch changes the naming of the mem_range attribute in SympleSystem to enable use of MemConfig for configuring the memory. Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4200 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-25configs,sim-se: fix se.py multi-cpu multi-cmd issuePau Cabre
Assign different pids to the different commands specified with the "--cmd" flag to configs/example/se.py Without this change, the following command line triggers a "fatal: _pid 100 is already used" error: command=$PWD/tests/test-progs/hello/bin/arm/linux/hello ./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command" Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4160 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-19configs, arm: add option to enable security extensionsGedare Bloom
Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3264 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-18configs: fix cpu names in big.LITTLE examplePierre-Yves Péneau
CPU aliases have been dropped, this change fixes the big.LITTLE example. Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247 Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/3300 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-18arm, config: added support for ex5 model of big.LITTLEPierre-Yves Péneau
This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-09config: Fix up some configs to not use CPU aliases.Gabe Black
Support for CPU aliases were removed recently. Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f Reviewed-on: https://gem5-review.googlesource.com/3100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-06config: Remove support for CPU aliases.Gabe Black
This was added for backwards compatability, but it adds a decent amount of complexity. The table below shows what CPU class name to use in place of a given alias. +==========+========================================================+ | Alias | CPU class | +==========+========================================================+ | timing | TimingSimpleCPU | | atomic | AtomicSimpleCPU | | minor | MinorCPU | | detailed | DrivO3CPU | | kvm | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch | | trace | TraceCPU | +==========+========================================================+ Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08 Reviewed-on: https://gem5-review.googlesource.com/2940 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-11config, arm: Add an example power modelAndreas Sandberg
Add a script to demonstrate how power models can be wired to gem5 models. The script is meant as an example only and does not correlate with any realistic implementation. Change-Id: Ib95a74b2cb4af77a7816e3e8e89c89f3460775a1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2721 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-03config, arm: Add multi-core KVM support to bL configAndreas Sandberg
Add support for KVM in the big.LITTLE(tm) example configuration. This replaces the --atomic option with a --cpu-type option that can be used to switch between atomic, kvm, and timing simulation. When running in KVM mode, the simulation script automatically assigns separate event queues (threads) to each of the simulated CPUs. All simulated devices, including CPU child devices (e.g., interrupt controllers and caches), are assigned to event queue 0. Change-Id: Ic9a3f564db91f5a3d3cb754c5a02fdd5c17d5fdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2561 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03config, arm: Unify checkpoint path handling in bL configsAndreas Sandberg
The vanilla bL configuration file and the dist-gem5 configuration file use slightly different code paths when restoring from checkpoints. Unify this by passing the parsed options to the instantiate() method and adding an optional checkpoint keyword argument for checkpoint directories (only used by the dist-gem5 script). Change-Id: I9943ec10bd7a256465e29c8de571142ec3fbaa0e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2560 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
2017-02-14arm,config: Add dist-gem5 support to the big.LITTLE(tm) configGabor Dozsa
This patch extends the example big.LITTLE configuration to enable dist-gem5 simulations of big.LITTLE systems. Change-Id: I49c095ab3c737b6a082f7c6f15f514c269217756 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-14arm,config: Refactor the example big.LITTLE(tm) configurationGabor Dozsa
This patch prepares future extensions and customisation of the example big.LITTLE configuration script. It breaks out the major phases into functions so they can be called from other python scripts. Change-Id: I2cb7c207c410fe14602cf17af7482719abba6c24 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-14sim, kvm: make KvmVM a System parameterCurtis Dunham
A KVM VM is typically a child of the System object already, but for solving future issues with configuration graph resolution, the most logical way to keep track of this object is for it to be an actual parameter of the System object. Change-Id: I965ded22203ff8667db9ca02de0042ff1c772220 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-14mem: Update DRAM configuration namesWendy Elsasser
Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH> The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-01-09config: Fix missing include in fs.pyMatthias Jung
Bugfix for Elastic Traces This patch fixes the bug when elastic traces are used: build/ARM/gem5.opt \ configs/example/fs.py \ --cpu-type=arm_detailed \ --num-cpu=1 \ --mem-type=SimpleMemory \ --mem-size=512MB \ --mem-channels=1 \ --caches \ --elastic-trace-en \ --data-trace-file=data.proto.gz \ --inst-trace-file=inst.proto.gz \ --machine-type=VExpress_EMM \ --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \ --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \ --disk-image=linux-aarch32-ael.img NameError: global name 'CpuConfig' is not defined Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-12-06arm, config: Add missing IOCache in bL configGabor Dozsa
This patch adds an IOCache to the example bigLITTLE configuration. An IOCache is required for correct DMA transfers when we have caches in the system. Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-05config: Add an option to generate a random topology in memcheckNikos Nikoleris
This change adds the option to use the memcheck with random memory hierarchies at the moment limited to a maximum depth of 3 allowing testing with uncommon topologies. Change-Id: Id2c2fe82a8175d9a67eb4cd7f3d2e2720a809b60 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-12-05config: Add whole line accesses to improve memchecker's coverageNikos Nikoleris
Change-Id: Ie1a047139e350ce7400f3a20be644eaff1e21428 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-26gpu-compute: support in-order data delivery in GM pipeTony Gutierrez
this patch adds an ordered response buffer to the GM pipeline to ensure in-order data delivery. the buffer is implemented as a stl ordered map, which sorts the request in program order by using their sequence ID. when requests return to the GM pipeline they are marked as done. only the oldest request may be serviced from the ordered buffer, and only if is marked as done. the FIFO response buffers are kept and used in OoO delivery mode
2016-10-26config: Break out base options for usage with NULL ISAAndreas Hansson
This patch breaks out the most basic configuration options into a set of base options, to allow them to be used also by scripts that do not involve any ISA, and thus no actual CPUs or devices. The patch also fixes a few modules so that they can be imported in a NULL build, and avoid dragging in FSConfig every time Options is imported.
2016-10-14config: Make configs/common a Python packageAndreas Hansson
Continue along the same line as the recent patch that made the Ruby-related config scripts Python packages and make also the configs/common directory a package. All affected config scripts are updated (hopefully). Note that this change makes it apparent that the current organisation and naming of the config directory and its subdirectories is rather chaotic. We mix scripts that are directly invoked with scripts that merely contain convenience functions. While it is not addressed in this patch we should follow up with a re-organisation of the config structure, and renaming of some of the packages.
2016-10-13ruby: Fix regressions and make Ruby configs Python packagesAndreas Hansson
This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories. As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified.
2016-10-06config: add a separate config file for the network.Tushar Krishna
This patch adds a new file configs/network/Network.py to setup the network, instead of doing that within Ruby.py.
2016-10-06ruby: rename networktest to garnet_synthetic_traffic.Tushar Krishna
networktest is essentially a collection of synthetic traffic patterns for the network. The protocol name and the tester having the same name led to multiple python configuration files with the same name, adding confusion. This patch renames networktest to garnet_synthetic_traffic, and also adds more synthetic traffic patterns.
2016-09-15arm, config: Fixups for the example big.LITTLE(tm) configurationGabor Dozsa
This patch refactors the configuration file to use a more object-oriented design. Change-Id: I44ac2d063c2b5901f385544fb6ce3f259459cb05 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-08-22config: KVM acceleration for apu_se.pyDavid Hashe
Add support for using KVM to accelerate APU simulations. The intended use case is to fast-forward through runtime initialization until the first kernel launch.
2016-08-10arm, config: Add initial support for RubyAndreas Sandberg
Add initial support for creating an ARM system with a Ruby-based memory system. This support is currently experimental and limited to the new VExpress_GEM5_V1 platform. Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-07-21arm, config: Add an example ARM big.LITTLE(tm) configuration scriptGabor Dozsa
An ARM big.LITTLE system consists of two cpu clusters: the big CPUs are typically complex out-of-order cores and the little CPUs are simpler in-order ones. The fs_bigLITTLE.py script can run a full system simulation with various number of big and little cores and cache hierarchy. The commit also includes two example device tree files for booting Linux on the bigLITTLE system. Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-01mem: tester for new HMC configurationAbdul Mutaal Ahmad
This patch provides the example test script to configure different HMC architecture and run traffic through traffic generator. Committed by Jason Lowe-Power <jason@lowepower.com>
2016-06-09gpu-compute: parametrize Wavefront sizejkalamat
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work items); replaced it with a parameter in the GPU.py configuration script. Changed all data structures dependent on the Wavefront size to be dynamically sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at initialization time.
2016-04-21config: Add missing point of coherency to memcheck scriptAndreas Hansson
Bring in line with changes to the XBar class.
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
This patch introduces the ability of making the coherent crossbar the point of coherency. If so, the crossbar does not forward packets where a cache with ownership has already committed to responding, and also does not forward any coherency-related packets that are not intended for a downstream memory controller. Thus, invalidations and upgrades are turned around in the crossbar, and the memory controller only sees normal reads and writes. In addition this patch moves the express snoop promotion of a packet to the crossbar, thus allowing the downstream cache to check the express snoop flag (as it should) for bypassing any blocking, rather than relying on whether a cache is responding or not.
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-01-22ruby: changed all references to numCPs to num-cpBrad Beckmann
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-07config: Updates for distributed gem5 simulationsGabor Dozsa
2015-12-17configs: Make the default memtest behaviour more complexAndreas Hansson
Add functional and uncacheable accesses by default.
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
This patch allows the ruby random tester to use ruby ports that may only support instr or data requests. This patch is similar to a previous changeset (8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets. This current patch implements the support in a more straight-forward way. Since retries are now tested when running the ruby random tester, this patch splits up the retry and drain check behavior so that RubyPort children, such as the GPUCoalescer, can perform those operations correctly without having to duplicate code. Finally, the patch also includes better DPRINTFs for debugging the tester.
2015-12-07config: Enable elastic trace capture and replay in se/fsRadhika Jagtap
This patch adds changes to the configuration scripts to support elastic tracing and replay. The patch adds a command line option to enable elastic tracing in SE mode and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out both instruction fetch and data dependency traces. The patch also enables configuring the TraceCPU to replay traces using the SE and FS script. The replay run is designed to resume from checkpoint using atomic cpu to restore state keeping it consistent with FS run flow. It then switches to TraceCPU to replay the input traces.
2015-11-22config: Added missing types to JSON/INI Python readerAndrew Bardsley
Added the missing types EthernetAddr and Current to the JSON/INI file reader example configs/example/read_config.py. Also added __str__ to EthernetAddr to make values appear in the same form in JSON an INI files.
2015-11-06config: Update memtest to stress test clean writebacksAndreas Hansson
This patch adds yet another twist to the memtest cache hierarchy, in that the writeback_clean option is toggled at every level to match the clusivity of the downstream cache.
2015-11-06config: Update memtest to stress test cache clusivityAndreas Hansson
This patch adds an new twist to the memtest cache hierarchy, in that it switches from mostly inclusive to mostly exclusive at every level in the tree. This has helped weed out plenty issues, and serves as a good stress tests.
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