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2019-10-15configs: Add simpleSystem helper to generate devices.SimpleSystemGiacomo Travaglini
This patch will make it possible to generate a SimpleSystem inheriting from a configurable base class. More practically it will be possible to inherit from a baremetal System (ArmSystem) rather than from a LinuxArmSystem Change-Id: I11553ae8045519059e159c555c6c9141bb4519b7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21603 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07config: skip access to branchPred in ARM KVMCiro Santilli
Prevents runtime error: AttributeError: object 'ArmV8KvmCPU' has no attribute 'branchPred' Change-Id: Ic5765fd560381cbacc2fa2fd2e6f79d98433c535 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21299 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01configs: Port PlatformConfig to the common object listDaniel R. Carvalho
Port PlatformConfig to use the common object list. Change-Id: If62e596bf1f28b49994da3a2800450d163383755 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20593 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port MemConfig to the common object listDaniel R. Carvalho
Port MemConfig to use the common object list. Change-Id: If421c2745ac3431718a5170314045b456fc64a90 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-01configs: Port BPConfig to use the common object listDaniel R. Carvalho
Port BPConfig to use the common object list. Change-Id: I5cbd1c67cf743778bc59b5aa3c3dea5ab397b66d Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20590 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-30configs: Port CPUConfig to use the common object listDaniel R. Carvalho
Factor out ObjectList functionality from CPUConfig. Change-Id: I34ca55142e14559e584d38b6cca3aa5c20923521 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20589 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-21configs: root, platform options in fs bigLITTLEAdrian Herrera
(1) Two new options are added to fs_bigLITTLE.py: - "root": disk/partition containing the rootfs (def. "/dev/vda1") - "machine-type": hardware platform class (def. "VExpress_GEM5_V1") + Accepts platform classes from PlatformConfig (2) Default kernel is not available in public uploads, force the user to provide its own kernel instead of crashing. Change-Id: I88283ae12cd7289e15b9277ea2cc382e9136f11c Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20148 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-30configs, arch-arm: Check if gic has cpu_addr attributeChun-Chen TK Hsu
Add this check because Gicv3 does not have the cpu_addr attribute. Test: Change VExpress_GEM5_V1() to VExpress_GEM5_V2() and run the following command to boot Debian. M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py \ --dtb $PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb \ --kernel $PWD/fs_files/binaries/vmlinux \ --disk $PWD/fs_files/disks/disk.img \ --cpu-type atomic --big-cpus 1 --little-cpus 0 Change-Id: I23595ae5238dc7cc915ab09300f91aa5e8c24fdc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19648 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10configs: Fix read_config to work with new AddrRange serializationNikos Nikoleris
Change-Id: I122c77c34c2f8c75f8b32682be858f651112ce89 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19151 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10configs: Add python3 workarounds in read_configNikos Nikoleris
Change-Id: Ib065f41b87e5ada9535b9c2645067162aa69234b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19150 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31config, arm: memoryMode testWilly Wolff
Commit 9a13acaa367769c38859342de9bc35aac59a6710 doesn't comply with the same behaviour. The conditional test the memory mode on the same cluster, while it should test the other cluster. Change-Id: If3a7863f0905e66a548001d8e74689f5dd07179c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17748 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-17configs: Generalize FileSystemConfig for non se.pyJason Lowe-Power
This patch updates the FileSystemConfig so it works with more kinds of config scripts (e.g., the Learning gem5 scripts). There are 4 main changes: - Added system as a parameter to the config_filesystem function so the function can search the system for the number of CPUs instead of relying on options from Options.py - Instead of calling redirect_paths everywhere config_filesystem is used, now it is implicitly called. - Cleaned up the Ruby scripts a bit to remove redundant calls to config_filesystem - Added a config_filesystem call to the Ruby Learning gem5 script (currently the only Learning gem5 script that requires it). In the future, I think it would be better to move the config_filesystem call into simulate.py, probably into the instantiate function. I tried to use the per-CPU configuration parameters instead of options from Options.py, but that's not possible until after the SimObject params have been finalized in instantiate. Change-Id: Ie6501a7435cfb3ac9d2b45be3722388b34063b1e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18848 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-13config: add an option to list and select indirect branch predictorJairo Balart
Change-Id: I9a855d36de7d95b7785ff8a897899037cea6a3d8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25sim-se: add a faux-filesystemDavid Hashe
This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected. This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change). Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode. Change-Id: I90821b3b403168b904a662fa98b85def1628621c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22configs: Use param to get number of processorsPo-Hao Su
Although the parameter np is the same as options.num_cpus. But we should get the number of processors from the parameters of the function. Change-Id: I3eb02d7c75ab35410b773b06001d1b145cdccd49 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18248 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-08configs: Removed redudant exec-style importRyan Gambord
garnet_synth_traffic.py imports common.Options on line 40, so exec'ing the Options.py file again seems redundant. It also runs Options.py as a script rather than a module, which throws ValueError: Attempted relative import in non-package due to the recent change to python3 imports. Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-25configs: Remove default kernel value from system creationDaniel R. Carvalho
Kernel was being set using a placeholder and then assigned the correct value. This would generate the following error if the placeholder file did not exist: 'IOError: Can't find file <placeholder> on path' This patch follows the same directions of commit 12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default values, forcing the user to properly configure the kernel. Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-18configs: Use absolute import pathsAndreas Sandberg
Use absoluate import paths to be Python 3 compatible. This also imports absolute_import from __future__ to ensure that Python 2.7 behaves the same way as Python 3. Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-26configs: Fix Python 3 iterator and exec compatibility issuesAndreas Sandberg
Python 2.7 used to return lists for operations such as map and range, this has changed in Python 3. To make the configs Python 3 compliant, add explicit conversions from iterators to lists where needed, replace xrange with range, and fix changes to exec syntax. This change doesn't fix import paths since that might require us to restructure the configs slightly. Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16002 Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-25systemc: Update the sc_main.py config to use m5.systemc.Gabe Black
Change-Id: I386970b5cf7ee1262b259abfb3b5e902ccea9991 Reviewed-on: https://gem5-review.googlesource.com/c/16568 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-13configs: simpoint-profile usable with NonCachingCPUs onlyGiacomo Travaglini
NonCachingCPU is replacing the Atomic+fastmem option. Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15935 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12systemc: config: Don't inject a custom argv[0] in sc_main.py.Gabe Black
argv[0] is already part of sys.argv, so we don't need to add an additional argument in front of sys.argv. The argv[0] which is used in gem5 config scripts is the name of the config script itself. While it might seem a little odd for the name of a systemc program to end in .py, it's as arbitrary as any other name, and generally shouldn't cause a problem. If some other more sophisticated mechanism for setting argv[0] is necessary, then the user can write a very slightly more complicated version of this script with additional logic. Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8 Reviewed-on: https://gem5-review.googlesource.com/c/16342 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-11systemc: configs: Add a very simple config which just runs sc_main.Gabe Black
This config will just run the sc_main function (which must have been provided in c++ somehow), passing through any of the scripts command line arguments to sc_main. Needing to do this sort of thing is common enough that there should be a canned config which supports it. Change-Id: I8f88ba4776b9ec919dd8145a58cd856e11ac4e77 Reviewed-on: https://gem5-review.googlesource.com/c/16287 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-07configs, arch-arm: Using AddrRange for Realview mem_regionsGiacomo Travaglini
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object. Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-07configs: Unifiy interpretation of Realview mem_regionsGiacomo Travaglini
In every arm platform which is making use of them, mem_regions are interpreted as a pair of start address and size. However arm SimpleSystem, which is using VExpress_GEM5_V1, is interpreting them as start address and end address. This patch is fixing this mismatch. Change-Id: I0b2a2193cd07fbc5430f233438269a9c7c353df9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16205 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-30configs: Enable DTB autogeneration in starter_fs.pyGiacomo Travaglini
This patch is removing hardcoded default DTBs in favour of common DTB autogeneration. Change-Id: I68fdc2a169bfa8e8657c9ed4e4e127957a08cca1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15959 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
This patch is rewriting the DTB autogeneration functions available in fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem so that other configuration scripts can make use of it. Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15958 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25configs: fs.py remove --generate-dtb and enable it by defaultCiro Santilli
The option is now enabled if neither --bare-metal nor --dtb-filename are given. This is what fs_bigLITTLE.py already did before this patch. Change-Id: I9179f8c9fa18edbd1e0f1a65ea2c1de0a26b7921 Reviewed-on: https://gem5-review.googlesource.com/c/15899 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
Added the parameter "--bp-type" to set the branch predictor type Added the parameter "--list-bp-types" to list all the available branch predictor types Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14015 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-09configs: Revamp ruby mem test to align with MemTestNikos Nikoleris
The test script was broken as it was based on an older version of MemTest, this changes revamps the creation of MemTest and removes parameters that are not any longer valid. Change-Id: Ib87369c1e4717c2da23e8108c72eec871e56f6ed Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13596 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-19config: add --param to fs.py, se.py and fs_bigLITTLE.pyCiro Santilli
The option allows to set SimObject params from the CLI. The existing config scripts have a large number of options that simply set a single SimObject parameter, and many still are not exposed. This commit allows users to pass arbitrary parameters from the command line to prevent the need for this kind of trivial option. Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944 Reviewed-on: https://gem5-review.googlesource.com/c/12985 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-09configs: Fix CPUClass typo in se.pyDaniel R. Carvalho
Change 719eb033fe435133abf15501c249eec10d1c861f added a typo to se.py that breaks simpoint simulation, which generates the following error: Traceback (most recent call last): File "<string>", line 1, in <module> File "/home/daniel/gem5/src/python/m5/main.py", line 435, in main exec filecode in scope File "./configs/example/se.py", line 217, in <module> if not CpuConfig.is_atomic_cpu(TestCPUClass): NameError: name 'TestCPUClass' is not defined Change-Id: Ideede8c96a40ee16af733c3d57b02b64f1a18d12 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13267 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-17config, arm, power: Example to report the power for the L2 CacheSherif Elhabbal
This patch add an example to demonstrate how to report the power for the L2 Cache of the big cluster separately ,it decouples the L2 contributions from the CPU power equation Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com> Change-Id: Idde43c8bcb10df9d44d20282eaf21ce87a9d3f58 Reviewed-on: https://gem5-review.googlesource.com/12684 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-03config: Move KVM CPU checking to CpuConfig helper moduleAndreas Sandberg
Both se.py and fs.py need to check if a CPU is a KVM CPU. This is somewhat involved since CPUs can be disabled at compile time. Enable better code reuse by moving it to the CpuConfig module. Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12418 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-03-20arch-arm, configs: Treat the bootloader rom as cacheable memoryNikos Nikoleris
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-06config: Switch from the print statement to the print function.Gabe Black
Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0 Reviewed-on: https://gem5-review.googlesource.com/8762 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-05config: remove dead code in fs.pyNayan Deshmukh
We have not added the --generate-dtb option for non-ARM systems and hence this case becomes dead code. It also leads to error on non-ARM systems as is tries to access a non existent field. Change-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5 Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/7801 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-29config, arm: enable device tree autogeneration for bigLITTLECurtis Dunham
Change-Id: Iaa5eeb3504b3ff9e46b6f592a06d6b833c830d83 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5969 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29config: Embed Device Tree generation in fs.py configGlenn Bergmans
Equips the fs.py config routine with an extra commandline option --generate-dtb that will generate a dtb file automatically before running the simulation. Only works with ARM systems and gives a warning if the simulated system is not of --machine-type VExpress_GEM5_V1. Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5968 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10configs: Fill in the cpu.isa field in etrace_replay.py since no default are ↵Chen Zou
provided now Change-Id: I5f337b9969820bd74ed67e576e2d1a8e4666ecdb Reviewed-on: https://gem5-review.googlesource.com/7021 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-08gpu-compute: call createThreads() on cpu objs in apu_se.pyTony Gutierrez
commit 8ad26e2688b8736f9290086bb4026cc7500429e9 cpu: Don't override ISA if provided by user removed the default ISA from the BaseCPU, and instead relies on createThreads() to initiate a default ISA if none is specified. the apu_se.py script, however does not call creatThreads() leading to a fatal when constructing CPU objects. this patch adds the appropriate calls to createThreads() inside apu_se.py. Change-Id: I16a5929454c59d68a3f1b7b3858c48a70cb76412 Reviewed-on: https://gem5-review.googlesource.com/7101 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-01-02config: Handle NULL simobject parameters in read_config.py.Gabe Black
Change-Id: If0f87e8ee37099be4d0f3567db4fc34f8467e409 Reviewed-on: https://gem5-review.googlesource.com/6943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-02config: Fix parsing AddrRange parameters in read_config.py.Gabe Black
The format of AddrRange parameters was changed, but config/example/read_config.py wasn't updated for the new format. Change-Id: Ie0da7aaa47c827bacc2b4f7f44929efd868b8794 Reviewed-on: https://gem5-review.googlesource.com/6942 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-02config: Add a --checkpoint-dir argument to read_config.py.Gabe Black
This argument lets the user restore a checkpoint after loading simulator state from config.ini. Change-Id: I6e0630d75b798a1d2536e2408660843f57f46c4b Reviewed-on: https://gem5-review.googlesource.com/6941 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet. Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2017-12-05config, mem, hmc: fix HMC test scriptÉder F. Zulian
This patch keeps the logic behind the HMC model implementation untouched. Additional changes: - simple hello world script using HMC (SE simulation) Usage examples: ./build/ARM/gem5.opt configs/example/hmctest.py ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=same ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=mixed ./build/ARM/gem5.opt configs/example/hmc_hello.py ./build/ARM/gem5.opt configs/example/hmc_hello.py --enable-global-monitor --enable-link-monitor Change-Id: I64eb6c9abb45376b6ed72722926acddd50765394 Reviewed-on: https://gem5-review.googlesource.com/6061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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