gem5 - gem5

Age	Commit message (Expand)	Author
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2011-07-26	Ruby: Fix instantiations of DMA controller and sequencer	Nilay Vaish
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-05-23	config: tweak ruby configs to clean up hierarchy	Steve Reinhardt
2011-04-28	network: convert links & switches to first class C++ SimObjects	Brad Beckmann
2011-03-25	ruby: fixed cache index setting	Brad Beckmann
2010-08-24	config: fixed ruby dma device connections	Brad Beckmann
2010-08-20	memtest: Memtester support for DMA	Brad Beckmann
2010-08-20	config: Improve ruby simobject names	Brad Beckmann
2010-08-20	config: reorganized how ruby specifies command-line options	Brad Beckmann
2010-08-20	config: moved python protocol config files	Brad Beckmann
2010-03-21	ruby: Reorganized Ruby topology and protocol files	Brad Beckmann
2010-03-21	ruby: Python config files now sets a unique id for each sequencer	Brad Beckmann
2010-01-29	ruby: MESI_CMP_directory updated to the new config system	Brad Beckmann