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path: root/configs/ruby/MOESI_hammer.py
AgeCommit message (Expand)Author
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
2015-08-30ruby: specify number of vnets for each protocolNilay Vaish
2015-08-14ruby: Protocol changes for SimObject MessageBuffersJoel Hestness
2015-08-14ruby: Remove the RubyCache/CacheMemory latencyJoel Hestness
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-10-11ruby: moesi hammer: correct typo in master-slave assignmentNilay Vaish
2014-09-01ruby: message buffers: significant changesNilay Vaish
2014-09-01ruby: Fixes clock domains in configuration filesEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2014-03-17config: ruby: remove piobus from protocolsNilay Vaish
2014-02-24ruby: correct errors in changeset 4eec7bdde5b0Nilay Vaish
2014-01-04ruby: remove cntrl_id from python config scripts.Nilay Vaish
2013-08-20ruby: add option for number of transitions per cycleNilay Vaish
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
2013-06-28ruby: check for compatibility between mem size and num dirsNilay Vaish
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-05-21ruby: moesi hammer: cosmetic changesNilay Vaish
2013-01-14config: move ruby objects under ruby_system in obj hierarchyMalek Musleh
2012-10-27Ruby: Use block size in configuring directory bits in addressJason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-08-16Ruby: Add RubySystem parameter to MemoryControlJason Power
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-02-14MEM: Fix master/slave ports in Ruby and non-regression scriptsAndreas Hansson
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
2012-01-07Ruby Cache: Add param for marking caches as instruction onlyNilay Vaish
2011-07-26Ruby: Fix instantiations of DMA controller and sequencerNilay Vaish
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
2011-04-28network: convert links & switches to first class C++ SimObjectsBrad Beckmann
2011-03-25ruby: fixed cache index settingBrad Beckmann
2011-02-06ruby: numa bit fix for sparse memoryBrad Beckmann
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann
2010-08-30config: minor fix to probe filter index settingBrad Beckmann
2010-08-24testers: move testers to a new directoryBrad Beckmann
2010-08-20ruby: Recycle latency fix for hammerBrad Beckmann
2010-08-20ruby: added probe filter support to hammerBrad Beckmann
2010-08-20ruby: Disable migratory sharing for token and hammerBrad Beckmann
2010-08-20ruby: Reduced ruby latenciesBrad Beckmann
2010-08-20memtest: Memtester support for DMABrad Beckmann
2010-08-20config: Improve ruby simobject namesBrad Beckmann
2010-08-20config: reorganized how ruby specifies command-line optionsBrad Beckmann
2010-08-20config: moved python protocol config filesBrad Beckmann
2010-03-21ruby: Reorganized Ruby topology and protocol filesBrad Beckmann
2010-03-21added sparse memory support to hammerBrad Beckmann
2010-03-21ruby: Python config files now sets a unique id for each sequencerBrad Beckmann