gem5 - gem5

Age	Commit message (Expand)	Author
2014-01-04	ruby: some small changes	Nilay Vaish
2013-12-20	ruby: mesi: remove owner and sharer fields from directory tags	Nilay Vaish
2013-09-06	ruby: network: correct naming of routers	Nilay Vaish
2013-08-20	ruby: add option for number of transitions per cycle	Nilay Vaish
2013-08-19	config: Move the memory instantiation outside FSConfig	Andreas Hansson
2013-06-28	ruby: check for compatibility between mem size and num dirs	Nilay Vaish
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Rename clock option to Ruby clock	Akash Bagdia
2013-05-21	ruby: moesi hammer: cosmetic changes	Nilay Vaish
2013-05-21	ruby: mesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp token: cosmetic changes	Nilay Vaish
2013-05-21	ruby: moesi cmp directory: cosmetic changes	Nilay Vaish
2013-05-21	configs: ruby: pass the option use_map to directory controller	Nilay Vaish
2013-04-17	config: ruby network test: remove piobus check	Nilay Vaish
2013-03-22	ruby: convert Topology to regular class	Nilay Vaish
2013-03-22	ruby: network: move routers from topology to network	Nilay Vaish
2013-03-06	ruby: garnet: fixed: implement functional access	Nilay Vaish
2013-01-14	config: move ruby objects under ruby_system in obj hierarchy	Malek Musleh
2012-12-11	ruby: add support for prefetching to MESI protocol	Nilay Vaish
2012-10-27	ruby: set the is_icache param for caches	Malek Musleh
2012-10-27	Ruby: Use block size in configuring directory bits in address	Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-02	ruby: changes to simple network	Nilay Vaish
2012-09-19	AddrRange: Simplify AddrRange params Python hierarchy	Andreas Hansson
2012-08-16	Ruby: Add RubySystem parameter to MemoryControl	Jason Power
2012-08-10	Ruby: Clean up topology changes	Jason Power
2012-07-10	ruby: changes how Topologies are created	Brad Beckmann
2012-04-06	ruby: set SimpleTiming as the default cpu	Brad Beckmann
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-04-05	Config: corrects the way Ruby attaches to the DMA ports	Nilay Vaish
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	Ruby: Connect system port in Ruby network test	Andreas Hansson
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-11	Ruby: Use map option for selecting b/w sparse and memory vector	Nilay Vaish
2012-01-10	Ruby: remove the files related to the tracer	Nilay Vaish
2012-01-07	Ruby Cache: Add param for marking caches as instruction only	Nilay Vaish
2011-12-01	config: command line option to specify ruby output file	gloh
2011-11-04	GARNET: adding a fault model for resilient on-chip network research.	Tushar Krishna
2011-07-26	Ruby: Fix instantiations of DMA controller and sequencer	Nilay Vaish
2011-07-25	Ruby: Fix dma controller configs/ruby/MI_example.py	Nilay Vaish
2011-07-03	Network_test: Conform it with functional access changes in Ruby	Nilay Vaish
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-05-23	config: tweak ruby configs to clean up hierarchy	Steve Reinhardt
2011-04-28	network: basic link bw for garnet and simple networks	Brad Beckmann
2011-04-28	network: convert links & switches to first class C++ SimObjects	Brad Beckmann