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2018-11-08configs: Add missing path to ruby importsDaniel R. Carvalho
Add missing addToPath to ruby files, so that import modules from previous folder are visible. Change-Id: I912d78a2f709974f72fe768e73abac1617126f46 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13995 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-10configs: Use the same address ranges for dir and mem_ctrlsNikos Nikoleris
In Ruby, for every directory we create one memory controller for every range in the memory ranges. Previously the memory controllers and the directories created their address ranges independently and as a result a mismatch was possible. In fact, we assinged an interleaved address range with hasing for the memory controllers while the corresponding directories would be assigned the same interleaved address range without hashing. This change uses the address range of the memory controllers to populate the list of address ranges for the corresponding directory and avoid bugs due to code duplication. Change-Id: I1e321c81a254199e5aaa9f3b81f4a4642c60a67a Reviewed-on: https://gem5-review.googlesource.com/12318 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
fixes line length and white space issues. Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3 Reviewed-on: https://gem5-review.googlesource.com/9801 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2018-03-20arch-arm, configs: Treat the bootloader rom as cacheable memoryNikos Nikoleris
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-06config: Switch from the print statement to the print function.Gabe Black
Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0 Reviewed-on: https://gem5-review.googlesource.com/8762 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-06-13ruby, arm: Forward invalidations to the local exclusive monitorNikos Nikoleris
ARM systems require local exclusive monitors for the implementation of synchronization primitives between processors. A ruby memory system needs to forward invalidations to the local exclusive monitors to to correctly determine their state. Change-Id: I7bc4d0f2a5be0f4e36a25c87aa4a81a3f086fb3c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2904 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-13ruby: Add support for address ranges in the directoryNikos Nikoleris
Previously the directory covered a flat address range that always started from address 0. This change adds a vector of address ranges with interleaving and hashing that each directory keeps track of and the necessary flexibility to support systems with non continuous memory ranges. Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2903 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-09config: Fix up some configs to not use CPU aliases.Gabe Black
Support for CPU aliases were removed recently. Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f Reviewed-on: https://gem5-review.googlesource.com/3100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2016-10-14config: Make configs/common a Python packageAndreas Hansson
Continue along the same line as the recent patch that made the Ruby-related config scripts Python packages and make also the configs/common directory a package. All affected config scripts are updated (hopefully). Note that this change makes it apparent that the current organisation and naming of the config directory and its subdirectories is rather chaotic. We mix scripts that are directly invoked with scripts that merely contain convenience functions. While it is not addressed in this patch we should follow up with a re-organisation of the config structure, and renaming of some of the packages.
2016-10-13ruby: Fix regressions and make Ruby configs Python packagesAndreas Hansson
This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories. As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified.
2016-10-06config: add a separate config file for the network.Tushar Krishna
This patch adds a new file configs/network/Network.py to setup the network, instead of doing that within Ruby.py.
2016-10-06ruby: rename ALPHA_Network_test protocol to Garnet_standalone.Tushar Krishna
Over the past 6 years, we realized that the protocol is essentially used to run the garnet network in a standalone manner, and feed standard synthetic traffic patterns through it.
2016-08-22config: KVM acceleration for apu_se.pyDavid Hashe
Add support for using KVM to accelerate APU simulations. The intended use case is to fast-forward through runtime initialization until the first kernel launch.
2016-08-10ruby: Implement support for functional accesses to PIO rangesAndreas Sandberg
There are cases where we want to put boot ROMs on the PIO bus. Ruby currently doesn't support functional accesses to such memories since functional accesses are always assumed to go to physical memory. Add the required support for routing functional accesses to the PIO bus. Change-Id: Ia5b0fcbe87b9642bfd6ff98a55f71909d1a804e3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com> Reviewed-by: Michael LeBeane <michael.lebeane@amd.com>
2016-01-22ruby: changed all references to numCPs to num-cpBrad Beckmann
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
This patch allows the ruby random tester to use ruby ports that may only support instr or data requests. This patch is similar to a previous changeset (8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets. This current patch implements the support in a more straight-forward way. Since retries are now tested when running the ruby random tester, this patch splits up the retry and drain check behavior so that RubyPort children, such as the GPUCoalescer, can perform those operations correctly without having to duplicate code. Finally, the patch also includes better DPRINTFs for debugging the tester.
2015-10-14ruby: profiler: provide the number of vnets through ruby systemNilay Vaish
The aim is to ultimately do away with the static function Network::getNumberOfVirtualNetworks().
2015-09-01ruby: remove random seedNilay Vaish
We no longer use the C library based random number generator: random(). Instead we use the C++ library provided rng. So setting the random seed for the RubySystem class has no effect. Hence the variable and the corresponding option are being dropped.
2015-08-30ruby: specify number of vnets for each protocolNilay Vaish
The default value for number of virtual networks is being removed. Each protocol should now specify the value it needs.
2015-08-21ruby: Move Rubys cache class from Cache.py to RubyCache.pyAndreas Hansson
This patch serves to avoid name clashes with the classic cache. For some reason having two 'SimObject' files with the same name creates problems. --HG-- rename : src/mem/ruby/structures/Cache.py => src/mem/ruby/structures/RubyCache.py
2015-08-19ruby: reverts to changeset: bf82f1f7b040Nilay Vaish
2015-08-14ruby: profiler: provide the number of vnets through ruby systemNilay Vaish
The aim is to ultimately do away with the static function Network::getNumberOfVirtualNetworks().
2015-08-14ruby: remove random seedNilay Vaish
We no longer use the C library based random number generator: random(). Instead we use the C++ library provided rng. So setting the random seed for the RubySystem class has no effect. Hence the variable and the corresponding option are being dropped.
2015-08-14ruby: Protocol changes for SimObject MessageBuffersJoel Hestness
2015-08-14ruby: Expose MessageBuffers as SimObjectsJoel Hestness
Expose MessageBuffers from SLICC controllers as SimObjects that can be manipulated in Python. This patch has numerous benefits: 1) First and foremost, it exposes MessageBuffers as SimObjects that can be manipulated in Python code. This allows parameters to be set and checked in Python code to avoid obfuscating parameters within protocol files. Further, now as SimObjects, MessageBuffer parameters are printed to config output files as a way to track parameters across simulations (e.g. buffer sizes) 2) Cleans up special-case code for responseFromMemory buffers, and aligns their instantiation and use with mandatoryQueue buffers. These two special buffers are the only MessageBuffers that are exposed to components outside of SLICC controllers, and they're both slave ends of these buffers. They should be exposed outside of SLICC in the same way, and this patch does it. 3) Distinguishes buffer-specific parameters from buffer-to-network parameters. Specifically, buffer size, randomization, ordering, recycle latency, and ports are all specific to a MessageBuffer, while the virtual network ID and type are intrinsics of how the buffer is connected to network ports. The former are specified in the Python object, while the latter are specified in the controller *.sm files. Unlike buffer-specific parameters, which may need to change depending on the simulated system structure, buffer-to-network parameters can be specified statically for most or all different simulated systems.
2015-08-14ruby: Remove the RubyCache/CacheMemory latencyJoel Hestness
The RubyCache (CacheMemory) latency parameter is only used for top-level caches instantiated for Ruby coherence protocols. However, the top-level cache hit latency is assessed by the Sequencer as accesses flow through to the cache hierarchy. Further, protocol state machines should be enforcing these cache hit latencies, but RubyCaches do not expose their latency to any existng state machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter is superfluous for all caches. This is confusing for users. As a step toward pushing L0/L1 cache hit latency into the top-level cache controllers, move their latencies out of the RubyCache declarations and over to their Sequencers. Eventually, these Sequencer parameters should be exposed as parameters to the top-level cache controllers, which should assess the latency. NOTE: Assessing these latencies in the cache controllers will require modifying each to eliminate instantaneous Ruby hit callbacks in transitions that finish accesses, which is likely a large undertaking.
2015-08-03ruby: correctly number the sequencer in MESI_Three_Level.pyNilay Vaish
2015-07-20config: add base class for ruby controllersDavid Hashe
The CntrlBase python class handles configuration parameters such as running counts of controllers and sequencers.
2015-07-20ruby: initialize replacement policies with their own simobjsDavid Hashe
this is in preparation for other replacement policies that take additional parameters.
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2015-07-04config: Update location of ruby topologies in helpDavid Hashe
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
Previously, the user would have to manually set access_backing_store=True on all RubyPorts (Sequencers) in the config files. Now, instead there is one global option that each RubyPort checks on initialization. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-01-20config, ruby: connect dma to networkMalek Musleh
DMA Controller was not being connected to the network for the MESI_Three_Level protocol as was being done in the other protocol config files. Without this patch, this protocol segfaults during startup. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-01-03configs: ruby: removes bug introduced by 05b5a6cf3521Nilay Vaish
2014-12-04config: ruby: mi protocol: correct master slave setting for dmaNilay Vaish
In the MI protocol, the master slave connection between the dma controller and network was being set incorrectly. This patch corrects it.
2014-11-23Backed out prior changeset f9fb64a72259Steve Reinhardt
Back out use of importlib to avoid implicitly creating dependency on Python 2.7.
2014-11-23config: ruby: Get rid of an "eval" and an "exec" operating on generated code.Gabe Black
We can get the same result using importlib.
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-11-06ruby: provide a backing storeNilay Vaish
Ruby's functional accesses are not guaranteed to succeed as of now. While this is not a problem for the protocols that are currently in the mainline repo, it seems that coherence protocols for gpus rely on a backing store to supply the correct data. The aim of this patch is to make this backing store configurable i.e. it comes into play only when a particular option: --access-backing-store is invoked. The backing store has been there since M5 and GEMS were integrated. The only difference is that earlier the system used to maintain the backing store and ruby's copy was write-only. Sometime last year, we moved to data being supplied supplied by ruby in SE mode simulations. And now we have patches on the reviewboard, which remove ruby's copy of memory altogether and rely completely on the system's memory to supply data. This patch adds back a SimpleMemory member to RubySystem. This member is used only if the option: access-backing-store is set to true. By default, the memory would not be accessed.
2014-11-06ruby: interface with classic memory controllerNilay Vaish
This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface.
2014-11-06ruby: single physical memory in fs modeNilay Vaish
Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby.
2014-10-11ruby: moesi hammer: correct typo in master-slave assignmentNilay Vaish
2014-09-01ruby: message buffers: significant changesNilay Vaish
This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work.
2014-09-01ruby: Fixes clock domains in configuration filesEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-19config: ruby: remove memory controller from network testNilay Vaish
It is not in use and not required as such.
2014-03-20ruby: garnet: convert network interfaces into clocked objectsNilay Vaish
This helps in configuring the network interfaces from the python script and these objects no longer rely on the network object for the timing information.
2014-03-20config: ruby: rename _cpu_ruby_ports to _cpu_portsNilay Vaish