gem5 - gem5

Age	Commit message (Expand)	Author
2016-10-14	config: Make configs/common a Python package	Andreas Hansson
2015-08-21	mem: Add explicit Cache subclass and make BaseCache abstract	Andreas Hansson
2015-03-02	mem: Move crossbar default latencies to subclasses	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2013-07-18	config: Update script to set cache line size on system	Andreas Hansson
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-02-14	MEM: Fix residual bus ports and make them master/slave	Andreas Hansson
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2010-10-22	Configs: Stop setting the "mem" parameter in splash2 config files.	Gabe Black
2010-08-17	sim: make Python Root object a singleton	Steve Reinhardt
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2007-06-30	Get rid of remaining traces of obsolete CoherenceProtocol object.	Steve Reinhardt
2006-11-13	Update splash2 config files	Ron Dreslinski