gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2013-07-18	config: Update script to set cache line size on system	Andreas Hansson
2013-06-27	config: Add a system clock command-line option	Akash Bagdia
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-02-14	MEM: Fix residual bus ports and make them master/slave	Andreas Hansson
2012-02-12	configs: fix minor config bugs posted on the mailing list	Ali Saidi
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2010-10-22	Configs: Stop setting the "mem" parameter in splash2 config files.	Gabe Black
2010-08-17	sim: make Python Root object a singleton	Steve Reinhardt
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2007-11-15	Configs: Fix for benchmarks that don't use getopt.	Ali Saidi
2007-11-15	Config: Fix some errors in the splash2 config file.	Ali Saidi
2007-06-30	Get rid of remaining traces of obsolete CoherenceProtocol object.	Steve Reinhardt
2007-04-23	Fix the splash2 run script	Ron Dreslinski
2006-11-13	Update splash2 config files	Ron Dreslinski
2006-11-12	Update for maxtick in splash2/memtest configs	Ron Dreslinski
2006-10-20	Add some default options, point it to the /dist version of the splash benchmarks	Ron Dreslinski
2006-10-20	Clean up splash2 so it works in v2.0	Ron Dreslinski
2005-06-04	Clean up to work with recent python config changes.	Steve Reinhardt
2005-06-01	A few more config updates. Works with regression now.	Steve Reinhardt
2005-03-16	Fixed the super/parent change fpr splash2 benchmarks	Ron Dreslinski
2005-03-11	Added config files for splash2 benchmarks. Parameters:	Ron Dreslinski