gem5 - gem5

Age	Commit message (Expand)	Author
2012-01-28	Config: Enable O3 CPU and Ruby in FS mode	Nilay Vaish
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-26	configs: actually add ARMv7a-like cpu/cache file	Ronald Dreslinski
2012-01-26	configs: A more realistic configuration of an ARM-like processor	Ronald Dreslinski
2012-01-25	MEM: Fix fs.py by specifying the range size rather than end	Andreas Hansson
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-11	Ruby: Use map option for selecting b/w sparse and memory vector	Nilay Vaish
2012-01-11	Config: Add support for restoring using a timing CPU	Nilay Vaish
2012-01-10	Ruby: remove the files related to the tracer	Nilay Vaish
2012-01-10	Config: Remove short option string for cpu type	Nilay Vaish
2012-01-09	ARM: Add support for running multiple systems	Ali Saidi
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-09	cpu2000: Add missing art benchmark to all	Ali Saidi
2012-01-07	Ruby Cache: Add param for marking caches as instruction only	Nilay Vaish
2012-01-05	Config: Add an option of type 'choice' for cpu type	Nilay Vaish
2011-12-15	ARM: Update config files for Android/BBench images available on website.	Anthony Gutierrez
2011-12-01	config: command line option to specify ruby output file	gloh
2011-12-01	VNC: Add support for capturing frame buffer to file each time it is changed.	Chris Emmons
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-11-04	GARNET: adding a fault model for resilient on-chip network research.	Tushar Krishna
2011-10-29	Ruby FS: Add the options for kernel and simulation script	Nilay Vaish
2011-10-19	ARM: Fix small bug in config script that prevents android from booting	Ali Saidi
2011-08-19	ARM: Add some MP regressions and clean up the disk images and kernels a bit	Ali Saidi
2011-08-19	ARM: Add VExpress_E support with PCIe to gem5	Ali Saidi
2011-08-19	ARM: Add support for Versatile Express boards	Ali Saidi
2011-08-02	Scons: Drop RUBY as compile time option.	Nilay Vaish
2011-07-26	Ruby: Fix instantiations of DMA controller and sequencer	Nilay Vaish
2011-07-25	Ruby: Fix dma controller configs/ruby/MI_example.py	Nilay Vaish
2011-07-11	se.py: Fixes the way ruby's options are added	Nilay Vaish
2011-07-03	Network_test: Conform it with functional access changes in Ruby	Nilay Vaish
2011-06-30	config: removed unnecessary slashes	Brad Beckmann
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom
2011-05-23	config: revamp x86 config to avoid appending to SimObjectVectors	Steve Reinhardt
2011-05-23	config: tweak ruby configs to clean up hierarchy	Steve Reinhardt
2011-05-23	configs: missed spot progress-interval change	Korey Sewell
2011-05-21	configs: remove -p from ruby_network_test.py	Tushar Krishna
2011-05-20	configs: cleanup redundant/unused options	Korey Sewell
2011-05-07	NetworkTest: added sim_cycles parameter to the network tester.	Tushar Krishna
2011-05-04	ARM: Configure bootloader parameters	Ali Saidi
2011-04-28	network: basic link bw for garnet and simple networks	Brad Beckmann
2011-04-28	network: convert links & switches to first class C++ SimObjects	Brad Beckmann
2011-04-20	python: fix another bug from changes to main.py	Nathan Binkert
2011-04-04	ARM: Include IDE/CF controller by default in PBX model.	Ali Saidi
2011-04-04	Sim: Fix Simulation.py to allow more than 1 core for standard switching.	Anthony Gutierrez