summaryrefslogtreecommitdiff
path: root/configs
AgeCommit message (Collapse)Author
2006-11-30netperf-maerts-client.rcS:Lisa Hsu
change /netperf/netperf to /netperf-bin/netperf nat-netperf-maerts-client.rcS: bad comment that went with the file - accidentally committed but probably doesn't matter, i ust eliminated an ivlb in the script. configs/boot/nat-netperf-maerts-client.rcS: replace netperf/netperf with netperf-bin/netperf configs/boot/netperf-maerts-client.rcS: change /netperf/netperf to /netperf-bin/netperf --HG-- extra : convert_revision : 32fed0042e267f315d3e688ebc4b66d7002b85f0
2006-11-26Include check for making sure caches are enabled.Kevin Lim
--HG-- extra : convert_revision : e3902b065db524ebe5bf762e44a840133ccb8d75
2006-11-16Implement a single config file to encompass all of the SPECNathan Binkert
CPU2000 stuff, and use it in all of the tests that currently use SPEC --HG-- extra : convert_revision : 8cd26a597e51a90b6d2810d344a075f5aa0f011b
2006-11-15Add L2 cache option to fs.py --l2cacheRon Dreslinski
--HG-- extra : convert_revision : 5bdd1129c3b23e91d441e7b83f6a824ef7740fab
2006-11-13Update splash2 config filesRon Dreslinski
configs/splash2/run.py: Fix MaxTick for splash configs configs/splash2/cluster.py: Add a config that allows clusters of CPU's to be attached to a single L1 --HG-- extra : convert_revision : 1bb0a0c5f4889316940a9858be90ae2eaa849f1a
2006-11-12Merge ktlim@zamp:./local/clean/tmp/test-regressKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
2006-11-12Update for maxtick in splash2/memtest configsRon Dreslinski
configs/example/memtest.py: configs/splash2/run.py: Update for maxtick --HG-- extra : convert_revision : 94106625be1ebc2b614db16720a4861e47222c0b
2006-11-10Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : 56cb7fe3be5b63bd89b48ac6cb88b47d13b4c137
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM ↵Ali Saidi
bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-09Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
2006-11-09Clean up config scripts to not have to worry about attaching a cache only to ↵Kevin Lim
the TimingCPU. Now the Atomic CPU works with caches. configs/common/Simulation.py: Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU. However the O3CPU must always use caches, so a check for that must still exist. Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU. configs/example/fs.py: configs/example/se.py: Atomic CPU now handles caches. --HG-- extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
2006-11-08simplify maxtick parsing in both the python and the c++.Lisa Hsu
configs/common/Simulation.py: simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick. src/python/m5/__init__.py: make a new m5 param called MaxTick. src/sim/host.hh: fix the M5 def. of MaxTick src/sim/main.cc: Simplify the MaxTick/num_cycles parsing within main.cc --HG-- extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
2006-11-08make rcS files read from the m5 source directory, not /dist.Lisa Hsu
--HG-- extra : convert_revision : 45a2dbf5b05b19dd60fbc3a5b10e9355c8351e3b
2006-11-08change to os.path.join like nate wanted.Lisa Hsu
--HG-- extra : convert_revision : 6e8a0153adf04f0cc07904434e4cb6a83fe900eb
2006-11-01factor some more commone code and enable going from checkpoint into ↵Lisa Hsu
arbitrary CPU with or without caches. configs/common/Simulation.py: enable going from checkpoint into arbitrary CPU with or without caches. --HG-- extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
2006-11-01make it so that you can do a standard switch without the caches option. ↵Lisa Hsu
this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache. --HG-- extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37
2006-11-01change name of 2nd switch_cpu so that ckpt recovery with multiple cpus ↵Lisa Hsu
doens't get confused. --HG-- extra : convert_revision : 16c710c4196c520d03c1993a26f38cf1f04ab637
2006-10-31Fix up configs.Kevin Lim
configs/common/Simulation.py: Remove mem parameter. configs/example/se.py: Remove debug output that got included in my other push. --HG-- extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
2006-10-31Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix configs/example/fs.py: configs/example/se.py: src/mem/tport.hh: Hand merge. --HG-- extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ↵Kevin Lim
for its MemObject instead of having to have a paramter for the MemObject. configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-30FSConfig.py:Lisa Hsu
Accidentally committed this last time configs/common/FSConfig.py: Accidentally committed this last time --HG-- extra : convert_revision : 32d49c17c661b57a9aa9c3b057258f6e037ba745
2006-10-30se.py, fs.py:Lisa Hsu
import Caches Simulation.py: Fix typo - L2Cache --> L1Cache configs/common/Simulation.py: Fix typo - L2Cache --> L1Cache configs/example/fs.py: configs/example/se.py: import Caches --HG-- extra : convert_revision : 4292225b322c069665262eab7c83b5341844fba0
2006-10-30ensure that there is a "/" between the cptdir and the cpt.%d.Lisa Hsu
--HG-- extra : convert_revision : 9aed7c3aecad10b039f3cfb26e04a7950be6bed1
2006-10-30Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : 836fcb45f399ed4f860be2d0bfe2ac4709bfe2ef
2006-10-30decouple the switch option from the warmup period option - parsing was ↵Lisa Hsu
confused otherwise, oops. --HG-- extra : convert_revision : 951fc664c59363df5f5e026aa791d83c26f050ec
2006-10-30Use some python os.path stuff to make it more flexible where we can execute ↵Kevin Lim
this script from. --HG-- extra : convert_revision : a76861a0f2669a7cd3bf3a34177739c69a913545
2006-10-30add some comments and make the warmup period in a switchover parameterizable.Lisa Hsu
configs/common/Options.py: make the warmup period in a standard switch part of the option. configs/common/Simulation.py: add some comments and also make the warmup period an option. --HG-- extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
2006-10-27factor out common run code from se.py and fs.py.Lisa Hsu
configs/example/fs.py: factor out common code. configs/example/se.py: factor out common code --HG-- extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
2006-10-24Fix fs.py. Lisa did you test this? Is there some wierd python version thing?Ali Saidi
--HG-- extra : convert_revision : 6df5f90d5b66e7af27d4f524744b9dc3c703a588
2006-10-23warmup of 1B cpu cycles.Lisa Hsu
configs/example/fs.py: configs/example/se.py: warm up of 1B CPU cycles --HG-- extra : convert_revision : 0f3263f466fde4cd86e0663930e83617a6b3faad
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
2006-10-23make a lot of the same changes as to fs.py for checkpointing.Lisa Hsu
1) rearrange the options to be in a nice logical order 2) add an option for what i call "standard switch", which is from simple->timing->detailed 3) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries. 4) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first --HG-- extra : convert_revision : 8d905e1b297ae664d60f8c8ba48b2aac25437fc6
2006-10-23changes regarding fs.pyLisa Hsu
1) rearrange the options to be in a nice logical order 2) add an option for what i call "standard switch", which is from simple->timing->detailed 3) change the client/server naming system to testsys/drivesys 4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries. 5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work. i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree. configs/example/fs.py: 1) rearrange the options to be in a nice logical order 2) add an option for what i call "standard switch", which is from simple->timing->detailed 3) change the client/server naming system to testsys/drivesys 4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries. 5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first --HG-- extra : convert_revision : 078e22800ff83f6e950bf5cc6fb16a98320e7c51
2006-10-22Add mutex test to Benchmarks.py.Steve Reinhardt
--HG-- extra : convert_revision : 9b4f1ce9a181ac5a01e5b6a68067079969dfe9ce
2006-10-20Add some default options, point it to the /dist version of the splash benchmarksRon Dreslinski
--HG-- extra : convert_revision : cd3b4f395b360d646b8b60464768eaad0fd110a4
2006-10-20Clean up splash2 so it works in v2.0Ron Dreslinski
configs/splash2/run.py: Update the splash2 file --HG-- extra : convert_revision : b57ef1ab4b8fd1eaf281358db623b7581b96546b
2006-10-20Give physical memory some latency to stress the systemRon Dreslinski
--HG-- extra : convert_revision : 3ca32ff9140770d0774cac5e82807a0574db09dd
2006-10-20Add a config file in the example with the memtester and some parser options.Ron Dreslinski
--HG-- extra : convert_revision : e70ccc3de4f7a3ae20ff9ec672853ee1555ed41b
2006-10-19First cut at LL/SC support in caches (atomic mode only).Steve Reinhardt
configs/example/fs.py: Add MOESI protocol to caches (uni coherence not quite working w/FS yet). --HG-- extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
2006-10-17Add --caches option to add caches to server CPUs.Steve Reinhardt
--HG-- extra : convert_revision : 6aa97dcc807e175215e73c638faf73be926d4cd4
2006-10-17Enable MP systems via cmd-line flag in fs.py.Steve Reinhardt
configs/example/fs.py: Add flag for MP server systems. src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/IntrControl.py: Change CPU from 'any' to 'cpu[0]' to work better with MP sytems. tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-timing-dual.py: Don't need to set console & intrcontrol cpu params anymore (default is fixed now). --HG-- extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
2006-10-17Rename 'Machine' to 'SysConfig'.Steve Reinhardt
Clean up a little. --HG-- extra : convert_revision : db5f36776209c76a593205c46b08aa147358f33a
2006-10-10Two minor fixes.Kevin Lim
configs/common/SysPaths.py: Undo accidental change. src/SConscript: Fix. --HG-- extra : convert_revision : 665b186cff7d8ae560601ced7ae407a41a16cfea
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/cpu/simple/timing.hh: tests/configs/o3-timing-mp.py: Hand merge. --HG-- extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09add in checkpoint restoration option, you can restore a checkpoint by giving ↵Lisa Hsu
a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd. so you can restore by a command line like this: m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3 configs/example/fs.py: add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. --HG-- extra : convert_revision : bf9c8d3265a3875cdfb6a878005baa7ae29af90d
2006-10-08Set cpu_id params (required by ll/sc code now).Steve Reinhardt
--HG-- extra : convert_revision : e0f7ccbeccca191a8edb54494d2b4f9369e9914c
2006-10-08Clean up configs.Kevin Lim
configs/common/FSConfig.py: configs/common/SysPaths.py: configs/example/fs.py: configs/example/se.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: Clean up configs by removing FullO3Config and instead using default values. src/python/m5/objects/FUPool.py: Add in default FUPool. src/python/m5/objects/O3CPU.py: Use defaults better. Also set checker parameters, and fix up a config bug. --HG-- extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-06add an option for defining a directory in which to place all your ↵Lisa Hsu
checkpoints. if none, default is cwd. --HG-- extra : convert_revision : 23a602c2d800c922346c9743cc0c583d178a0ee7
2006-10-05fix the argument to m5.simulate() on a checkpoint.Lisa Hsu
src/sim/stat_control.cc: add curTick to reset stats printf. --HG-- extra : convert_revision : da8cf5921e81b73f47d6831d539ca1fbdace3d1d
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 04:59:15 +0000