gem5 - gem5

Age	Commit message (Expand)	Author
2015-12-04	arm, config: Automatically discover available platforms	Andreas Sandberg
2015-11-22	config: Added missing types to JSON/INI Python reader	Andrew Bardsley
2015-11-22	config: Minor fixes to the DRAM utilisation sweep	Andreas Hansson
2015-11-06	config: Update memtest to stress test clean writebacks	Andreas Hansson
2015-11-06	mem: Add an option to perform clean writebacks from caches	Andreas Hansson
2015-11-06	config: Update memtest to stress test cache clusivity	Andreas Hansson
2015-11-06	mem: Add cache clusivity	Andreas Hansson
2015-11-04	configs: fix bug introduced due to 276ad9121192	Nilay Vaish
2015-11-03	mem: hmc: top level design	Erfan Azarkhish
2015-11-03	sparc: add missing parameter to makeSparcSystem()	Palle Lyckegaard
2015-10-14	ruby: profiler: provide the number of vnets through ruby system	Nilay Vaish
2015-10-01	config: Fix 'learning gem5' configs after SMT push	Andreas Hansson
2015-09-30	isa,cpu: Add support for FS SMT Interrupts	Mitch Hayenga
2015-09-30	config,cpu: Add SMT support to Atomic and Timing CPUs	Mitch Hayenga
2015-09-25	util: Fix minor issues in DRAM sweep scripts	Andreas Hansson
2015-09-16	config: Add configs scripts used in Learning gem5	Jason Lowe-Power
2015-09-06	config: allow ruby to be used with Minor CPU	Nilay Vaish
2015-09-01	ruby: remove random seed	Nilay Vaish
2015-08-30	ruby: specify number of vnets for each protocol	Nilay Vaish
2015-08-21	mem: Add explicit Cache subclass and make BaseCache abstract	Andreas Hansson
2015-08-21	ruby: Move Rubys cache class from Cache.py to RubyCache.py	Andreas Hansson
2015-08-19	ruby: reverts to changeset: bf82f1f7b040	Nilay Vaish
2015-08-14	ruby: profiler: provide the number of vnets through ruby system	Nilay Vaish
2015-08-14	ruby: remove random seed	Nilay Vaish
2015-08-14	ruby: Protocol changes for SimObject MessageBuffers	Joel Hestness
2015-08-14	ruby: Expose MessageBuffers as SimObjects	Joel Hestness
2015-08-14	ruby: Remove the RubyCache/CacheMemory latency	Joel Hestness
2015-08-03	misc: Coupling gem5 with SystemC TLM2.0	Matthias Jung
2015-08-03	ruby: correctly number the sequencer in MESI_Three_Level.py	Nilay Vaish
2015-07-20	config: add base class for ruby controllers	David Hashe
2015-07-20	ruby: initialize replacement policies with their own simobjs	David Hashe
2015-07-21	configs: network test: remove redundant physical memory	Nilay Vaish
2015-07-10	ruby: remove extra whitespace and correct misspelled words	Brandon Potter
2015-07-04	config: Update location of ruby topologies in help	David Hashe
2015-07-03	mem: Remove redundant is_top_level cache parameter	Andreas Hansson
2015-07-03	mem: Allow read-only caches and check compliance	Andreas Hansson
2015-06-01	kvm, arm: Add support for aarch64	Andreas Sandberg
2015-05-15	config: Use null memory for DRAM sweep script	Andreas Hansson
2015-05-15	config: Add new MemConfig options to DRAM sweep script	Wendy Elsasser
2015-05-05	arch, cpu: Do not forward snoops to table walker	Andreas Hansson
2015-04-29	cpu: o3: replace issueLatency with bool pipelined	Nilay Vaish
2015-04-23	config: enable setting SE-mode environment variables from file	bpotter
2015-04-20	config: Remove memory aliases and rely on class name	Andreas Hansson
2015-04-14	config, cpu: fix progress interval for switched CPUs	Malek Musleh
2015-04-13	cpu: re-organizes the branch predictor structure.	Dibakar Gope
2015-04-08	config: Support full-system with SST's memory system	Curtis Dunham
2015-03-27	arm, configs: Do not forward snoops from I cache	Andreas Hansson
2015-03-23	config: expand '~' and '~user' in paths	Steve Reinhardt
2015-03-23	config: Add ability to exit simulation after initialization	Curtis Dunham
2015-03-19	config: Add soak test for memtest.py	Andreas Hansson