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configs/test/SysPaths.py:
remove some tabs and add /n/poolfs/z/dist/m5/system
src/dev/io_device.cc:
fix since pio timing dma packts colud be nacked too
src/dev/io_device.hh:
move DmaReqState into DmaDevie
--HG--
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configs/test/SysPaths.py:
Make the paths more configurable
--HG--
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that's already being used for "detailed cpu".
Needed to add extra function for user script
to pass parsed options back to m5 module.
configs/test/fs.py:
configs/test/test.py:
Call setStandardOptions().
src/python/m5/__init__.py:
Add --outdir option.
Add setStandardOptions() so user script can
pass parsed options back to m5 module.
src/sim/main.cc:
Add SWIG-wrappable function to set output dir.
--HG--
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--HG--
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
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pretty simple so they shouldn't cause any trouble.
First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model.
Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled.
SConstruct:
Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled.
configs/test/test.py:
Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick.
src/base/traceflags.py:
Add in O3CPU trace flag.
src/cpu/SConscript:
Rename AlphaFullCPU to AlphaO3CPU.
Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included.
src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU.
src/cpu/cpu_models.py:
src/cpu/o3/alpha_cpu.cc:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_builder.cc:
src/cpu/o3/alpha_cpu_impl.hh:
Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model.
src/cpu/o3/alpha_dyn_inst.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/alpha_impl.hh:
src/cpu/o3/alpha_params.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
src/cpu/o3/thread_state.hh:
src/python/m5/objects/AlphaO3CPU.py:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
Rename FullCPU to O3CPU to differentiate from old FullCPU model.
Also #ifdef the checker code so it doesn't need to be included if it's not selected.
--HG--
rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc
rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc
rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py
extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.
configs/test/fs.py:
Add ".port" to busses to get a port reference.
Get rid of commented-out code.
src/python/m5/__init__.py:
resolveSimObject should call getCCObject() instead of createCCObject()
to avoid cycles in recursively creating objects.
src/python/m5/config.py:
Get rid of class/instance thing and go back to instance cloning.
Deep copy has to happen only on instance cloning then (and not on subclassing).
Add getCCObject() method to force creation of C++ SimObject without
recursively creating its children.
Add support for cloning port references (trickier than it sounds).
Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
Add ports.
--HG--
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--HG--
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--HG--
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src/arch/mips/isa/formats/trap.isa:
Take out fix that tried to fix trap
instruction disassembly. It forces bad
compile ..
configs/test/test.py:
add 'cycle' to exit message
--HG--
extra : convert_revision : 568877797fd2806416b4cbb388cc3f7eb2492627
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into Python.
Add Port and VectorPort objects and support for
specifying port connections via assignment.
The whole C++ ConfigNode hierarchy is gone now, as are
C++ Connector objects.
configs/test/fs.py:
configs/test/test.py:
Rewrite for new port connector syntax.
src/SConscript:
Remove unneeded files:
- mem/connector.*
- sim/config*
src/dev/io_device.hh:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/mem_object.hh:
src/mem/physical.cc:
src/mem/physical.hh:
Allow getPort() to take an optional index to
support vector ports (eventually).
src/python/m5/__init__.py:
Move SimObject construction and port connection
operations into Python (with C++ calls).
src/python/m5/config.py:
Move SimObject construction and port connection
operations into Python (with C++ calls).
Add support for declaring and connecting MemObject
ports in Python.
src/python/m5/objects/Bus.py:
src/python/m5/objects/PhysicalMemory.py:
Add port declaration.
src/sim/builder.cc:
src/sim/builder.hh:
src/sim/serialize.cc:
src/sim/serialize.hh:
ConfigNodes are gone; builder just gets the
name of a .ini file section now.
src/sim/main.cc:
Move SimObject construction and port connection
operations into Python (with C++ calls).
Split remaining initialization operations into two parts,
loadIniFile() and finalInit().
src/sim/param.cc:
src/sim/param.hh:
SimObject resolution done globally in Python now
(not via ConfigNode hierarchy).
src/sim/sim_object.cc:
Remove unneeded #include.
--HG--
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--HG--
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bcak to main LiveProcess, then automatically select
ISA based on object file type. Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().
configs/test/test.py:
Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
Move create() from arch-specific files back to
main LiveProcess, then automatically select ISA
based on object file type.
--HG--
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after the class has been instantiated or subclassed.
This is one of the main situations that leads to
confusing results.
configs/test/fs.py:
Clean up to avoid modifying BaseCPU after it's been subclassed.
--HG--
extra : convert_revision : 335cb87bc3b211ecc8969cfb99ffc28f62f1f877
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Minor fixes to ALPHA_FS and SPARC_SE.
SPARC_SE still does not compile... looks like there
are unresolved issues with ExecContext -> ThreadContext
rename/reorg.
configs/test/fs.py:
Port to new script interface/model.
configs/test/test.py:
Add support for running MIPS test(s) too via
command-line option.
src/arch/alpha/ev5.cc:
Fix include file.
src/arch/sparc/regfile.hh:
Make Bit64 a ULL constant to avoid compiler error.
--HG--
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User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.
SConstruct:
Set up SWIG builder & scanner.
Set up symlinking of source files into build directory
(by not disabling the default behavior).
configs/test/test.py:
Rewrite to use new script-driven interface.
Include a sample option.
src/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
SimExit() is now exitSimLoop().
src/cpu/base.cc:
SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
Add SWIG build command for main.i.
Use python/m5 in build dir as source for zip archive...
easy now with file duplication enabled.
src/python/m5/__init__.py:
- Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
- Get rid of argument parsing code; just provide default
option descriptors for user script to call optparse with.
- Don't clutter m5 namespace by sucking in all of m5.config
and m5.objects.
- Move instantiate() function here from config.py.
src/python/m5/config.py:
- Move instantiate() function to __init__.py.
- Param.Foo deferred type lookups must use m5.objects
namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
Support for Python-called simulate() function:
- Use IsExitEvent flag to signal events that want
to exit the simulation loop gracefully (instead of
calling exit() to terminate the process).
- Modify interface to hand exit event object back to
caller so it can be inspected for cause.
src/sim/host.hh:
Add MaxTick constant.
src/sim/main.cc:
Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
Use PYTHONPATH environment var to set module path
(instead of clunky code injection method).
Move main control from here into Python:
- Separate initialization code and simulation loop
into separate functions callable from Python.
- Make Python interpreter invocation more pure (more
like directly invoking interpreter).
Add -i and -p flags (only options on binary itself;
other options processed by Python).
Import readline package when using interactive mode.
src/sim/sim_events.cc:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
src/sim/sim_events.hh:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
Get rid of a few unused constructors.
src/sim/sim_exit.hh:
SimExit() is now exitSimLoop().
Get rid of unused functions.
Add comments.
--HG--
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SConscript:
Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
Fix paths.
configs/test/fs.py:
SimpleCPU -> AtomicSimpleCPU
Fix vmlinux path
cpu/simple/atomic.cc:
Fix suspendContext() so quiesce works.
Don't forget to checkForInterrupts().
cpu/simple/base.cc:
Minor fix to interrupt check code.
dev/ide_disk.hh:
Don't declare regStats() in header since it's not in
.cc file anymore (will need to add it back in when
stats are added back).
dev/io_device.cc:
Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
Set PCI config packet result to Success.
python/m5/objects/Root.py:
Add debug object to Root so things like break_cycles
can be set from command line.
--HG--
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TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.
arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.
--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
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Now we are to the point where more benchmarks and instruction-coverage
is necessary to totally verify/validate correct operation across
all MIPS instructions
arch/mips/isa_traits.hh:
fix for reading double values ... must rearrange bits before using void* to read double.
configs/test/hello_mips:
real hello world MIPS binary
--HG--
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into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem
--HG--
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Edit the convert_and_round function which access FloatRegFile
arch/isa_parser.py:
recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately
arch/mips/isa/decoder.isa:
Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the
bit manipulation ourselves. We can just concern ourselves with values.
Use unsigned double to get movd...
arch/mips/isa/formats/fp.isa:
float debug statement
arch/mips/isa_traits.cc:
add different versions of convert_and_round functions
arch/mips/isa_traits.hh:
Use an array of uint32_t unsigned integers to represent the Floating Point Regfile
configs/test/hello_mips:
basic FP program
cpu/simple/cpu.hh:
spacing
--HG--
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into zeep.pool:/z/saidi/work/m5.newmem
--HG--
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configs/test/fs.py:
update fs.py to use a bus bridge
cpu/simple/cpu.hh:
cpu should just return that it doesn't snoop any address ranges
python/m5/objects/System.py:
move boot_osflags to system
--HG--
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into ewok.(none):/home/gblack/m5/newmem
cpu/simple/cpu.cc:
Hand merged
--HG--
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--HG--
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timing packets working and get sinic working
after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.
SConscript:
add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
add nics to fs.py
cpu/cpu_exec_context.cc:
remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
use new methods for accessing packet data
dev/ide_disk.cc:
add some more dprintfs
dev/io_device.cc:
delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
dUpdate for new packet methods to access data
dev/ns_gige.cc:
Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
update for new memory system
dev/sinic.cc:
dev/sinic.hh:
Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
Add methods to access data instead of accessing it directly.
--HG--
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SConscript:
compile ide devices
base/chunk_generator.hh:
add another parameter to the chuck generator called complete() which
returns the number of bytes transfered so far. Very useful for
adding to a pointer.
configs/test/fs.py:
Add ide disk to fs test configuration
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
update for new memory system
mem/bus.cc:
support devices that return multiple ranges
remove old ranges before using new info
mem/packet.hh:
make senderstate void* per steve's request that we use every
construct possible in C++
mem/physical.cc:
have memory stamp the packet with the time.
mem/physical.hh:
actually set the memory latency variable
python/m5/objects/Device.py:
Add DmaDevice
python/m5/objects/Ide.py:
Ide disk no longer has a physmem pointer
python/m5/objects/Pci.py:
update pci device for newmem
python/m5/objects/PhysicalMemory.py:
add latency parameter for physical memory
sim/byteswap.hh:
use fast architecture dependent byteswap calls if they exist
--HG--
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--HG--
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Time to make the ide device work
arch/alpha/system.cc:
write the machine type and rev in the correct place
cpu/simple/cpu.cc:
reset the packet structure every time it's reused... wow the
simple cpu code for talking to memory is getting horrible.
dev/alpha_console.cc:
move the setAlphaAccess to startup() to make sure that the console
binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
More verbose bus tracing
mem/packet.hh:
Add a constructor to packet to set the result to unknown and a reset
method in the case it's being reused
mem/vport.hh:
don't need are own read/write methods since the base functional port
ones call writeBlob readBlob which do the translation for us
--HG--
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--HG--
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in the InstObjParams constructor.
arch/isa_parser.py:
Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
Added SPARC traceflag
configs/test/hello_sparc:
Recompiled without -mflat
cpu/cpu_exec_context.cc:
Used the regfile clear function rather than memsetting to 0.
--HG--
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arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
A test program for SPARC which prints "Hello World!"
--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
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--HG--
extra : convert_revision : 111af292373edebcd106938e76610f9ac4a6ce58
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--HG--
extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b
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into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
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is changed
Add a default machine width parameter
Arch based live processes
arch/alpha/linux/process.cc:
arch/alpha/linux/process.hh:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
arch/alpha/tru64/process.hh:
arch/mips/linux_process.cc:
arch/mips/process.cc:
arch/mips/process.hh:
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
arch/sparc/process.cc:
arch/sparc/process.hh:
configs/test/test.py:
python/m5/objects/Process.py:
sim/process.cc:
sim/process.hh:
Architecture based live processes
arch/mips/isa_traits.hh:
arch/sparc/isa_traits.hh:
Add a default machine width parameter
mem/port.hh:
gcc 4 really wants a virtual destructor
sim/byteswap.hh:
remove the comment around long and unsigned long even though uint32_t
and int32_t are defined. Seems to work with gcc 4 and 3.4.3.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
add translations for new sections that are mmapped or when the brk
is changed
--HG--
extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
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configs/test/hello_mips:
hello world mips binary
--HG--
extra : convert_revision : 5a495e1bfb1cbddc0879f8e80c02bd7435a02acb
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on execution.
configs/test/test.py:
Move test binary out of m5-test, don't depend on
m5-test/Benchmarks.
python/m5/objects/System.py:
Split out full-system-only parameters (lost in merge).
sim/system.cc:
Need to be able to instantiate System directly in SE mode
(lost in merge).
sim/system.hh:
A few more functions here are FS-only.
configs/test/hello:
Add in binary.
--HG--
rename : configs/test.py => configs/test/test.py
extra : convert_revision : 4051b18772e0a0dcb97eb591d4373683be9f4395
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See configs/test.py for test config (using simple
binary in my home directory on zizzer).
base/chunk_generator.hh:
Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
Fix roundDown to take integer alignments.
cpu/base.cc:
Register exec contexts regardless of state (not sure why
this check was in here in the first place).
mem/physical.cc:
Add breaks to switch.
python/m5/objects/BaseCPU.py:
Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
HierParams is gone.
python/m5/objects/PhysicalMemory.py:
mmu param is full-system only.
sim/process.cc:
Stack mapping request must be page-aligned and page-sized.
Don't delete objFile object in create since we are counting
on it being around for startup().
--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7
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variable
--HG--
extra : convert_revision : 2cb20845cb7f32589882850156bdd42d9024db7a
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configs/boot/iscsi-client.rcS:
Clean up the newly updated iscsi-client script.
Reduce the writeback period so writes occur more frequently.
--HG--
extra : convert_revision : 21c84f781c6537b28c753291561d23c2d0144627
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--HG--
extra : convert_revision : 0c12033b38e32f8b2ea69b52813dfed294ec5de4
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configs/boot/iscsi-client.rcS:
configs/boot/nfs-client-dbench.rcS:
don't use the /proc/m5 stuff, use the m5 binary
configs/boot/nfs-client-nhfsstone.rcS:
set up checkpoints
change nhfsstone configuration
configs/boot/nfs-client.rcS:
use more memory
configs/boot/nfs-server.rcS:
change the writeback frequency
load a larger simulated disk image.
create more nfsd threads
--HG--
extra : convert_revision : 242dfd261d62782c06847d64b9f6aa06664a1ec9
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--HG--
extra : convert_revision : 71e416668f4bbcf9785ea2363ec406135a217e32
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configs/splash2/run.py:
parent is now Parent.
Need to explicitly instantiate classes.
--HG--
extra : convert_revision : c260fad00ca82cb1032e73af2e5caa2ad013067d
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configs/splash2/run.py:
Update file for new config changes.
python/m5/config.py:
- isParamContext() not defined any more
- fix bug with re-assigning vectors over scalars
and vice versa
--HG--
rename : configs/splash2/run.mpy => configs/splash2/run.py
extra : convert_revision : 2eb28a92f8de327f6dfddd01467c61e759275f6b
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Delay before singalling peer to make sure that the peer is ready
configs/boot/nat-netperf-server.rcS:
delay before singalling to make sure that the natbox is ready
configs/boot/nat-netperf-stream-client.rcS:
increase the number of tracked connections
configs/boot/nat-spec-surge-client.rcS:
configs/boot/nfs-client-nhfsstone.rcS:
configs/boot/nfs-client-smallb.rcS:
configs/boot/nfs-client-tcp-smallb.rcS:
configs/boot/nfs-client-tcp.rcS:
configs/boot/nfs-client.rcS:
configs/boot/nfs-server.rcS:
configs/boot/spec-surge-client.rcS:
configs/boot/spec-surge-server.rcS:
configs/boot/surge-client.rcS:
configs/boot/surge-server.rcS:
increase the number of tracked connections
cleanup
configs/boot/nat-spec-surge-server.rcS:
configs/boot/natbox-netperf.rcS:
configs/boot/nfs-server-nhfsstone.rcS:
delay before singalling to make sure that the natbox is ready
increase the number of tracked connections
cleanup
configs/boot/natbox-spec-surge.rcS:
delay before singalling to make sure that the natbox is ready
increase the number of tracked connections
--HG--
extra : convert_revision : 9faa5ec11c9c02fed3d1cff922ca42c41d364204
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--HG--
extra : convert_revision : bda54b29cb15144907b186f06517477dea13ba06
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--HG--
extra : convert_revision : b454144b3c00c101e970269c6c084d601cee971f
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