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2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-16inorder-configs: update se.pyKorey Sewell
fix bug with 'numThreads=len(workloads)' which was counting characters of command-line not counting threads as intended. Update numThreads for inorder/o3 cases and default to 1 for all other cases.
2009-09-16configs: add maxinsts option on command lineKorey Sewell
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of cases then always having to figure out what tick to run your simulation to.
2009-09-14Add an I/O cache to FS config even if there's just an "L2" cache.Steve Reinhardt
2009-07-26se-configs: edit se.py to account for non-O3CPU workloadsKorey Sewell
2009-07-25o3-smt: enforce numThreads parameter for SMT SE modeKorey Sewell
2009-05-11ruby: Working M5 interface and updated Ruby interface.Daniel Sanchez
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu> RubyMemory is now both a driver for Ruby and a port for M5. Changed makeRequest/hitCallback interface. Brought packets (superficially) into the sequencer. Modified tester infrastructure to be packet based. and Ruby can be used together through the example ruby_se.py script. SPARC parallel applications work, and the timing *seems* right from combined M5/Ruby debug traces. To run, % build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-05cpus: fix cpu progress eventKorey Sewell
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-04-26X86, Config: Make makeX86System consider the number of CPUs, and clean up ↵Gabe Black
interrupt assignment.
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2009-04-21Minor tweaks for future Ruby compatibility.Steve Reinhardt
2009-04-19X86: Actually put the PCI INTA entry into the MP tables.Gabe Black
2009-04-19X86: Make E820 report nice, round (and correct) numbers.Gabe Black
2009-04-19X86: Automatically make the IO APIC in an N CPU system have id N+1.Gabe Black
2009-04-15configs: Allow M5_CPU2000 env var to set CPU2K binary path.Steve Reinhardt
It would be nice to have a more comprehensive mechanism but this is a big improvement over manually editing the script.
2009-02-25X86: Add IRQ4 to the Intel MP tables.Gabe Black
2009-02-10Configs: Add support for the InOrder CPU modelKorey Sewell
2009-02-01X86: Find the natural lpj for this configuration.Gabe Black
2009-02-01X86: Add a root device to the kernel command line.Gabe Black
2009-02-01X86: Configure the first PCI interrupt.Gabe Black
2009-02-01X86: Hook in a hard drive image.Gabe Black
2009-02-01X86: Take out the IDE noprobe kernel arguments.Gabe Black
2009-02-01X86: Plug in an IDE controller.Gabe Black
2009-01-31X86: Add some interrupt info to the intel MP tables.Gabe Black
2009-01-30Errors: Print a URL with a hash of the format string to find more ↵Ali Saidi
information about an error.
2009-01-25X86: Prevent Linux for probing for non-existant IDE controllers.Gabe Black
2008-10-11X86: Add entries for the IO APIC to the MP table.Gabe Black
2008-10-11X86: Add an Intel MP table to the simulation.Gabe Black
2008-10-11X86: Rename the PC device to Pc.Gabe Black
--HG-- rename : src/dev/x86/PC.py => src/dev/x86/Pc.py
2008-10-10X86: Turn SMBios structures into simobjects.Gabe Black
2008-10-10X86: Split makeLinuxX86System into makeLinuxX86System and makeX86System.Gabe Black
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵Ali Saidi
should configure their editors to not insert tabs
2008-07-23process: separate stderr from stdoutMichael Adler
- Add the option of redirecting stderr to a file. With the old behaviour, stderr would follow stdout if stdout was to a file, but stderr went to the host stderr if stdout went to the host stdout. The new default maintains stdout and stderr going to the host. Now the two can specify different files, but they will share a file descriptor if the name of the files is the same. - Add --output and --errout options to se.py to go with --input.
2008-06-17Rename SimConsole to Terminal since it makes more senseNathan Binkert
--HG-- rename : src/dev/SimConsole.py => src/dev/Terminal.py rename : src/dev/simconsole.cc => src/dev/terminal.cc rename : src/dev/simconsole.hh => src/dev/terminal.hh
2008-06-13Scripts: Check for the appropriate build type as soon as possible.Ali Saidi
2008-06-12X86: Make the e820 table manually or automatically configurable from python.Gabe Black
2008-06-12X86: Force the kernel to use a certain loops per jiffy instead of ↵Gabe Black
calculating it.
2008-06-12X86: Make the amount of system memory match the hardcoded e820 info.Gabe Black
2008-06-12X86: Make the regular console use the serial port as well.Gabe Black
2008-03-25X86: Change the Opteron platform to be the PC platform.Gabe Black
--HG-- extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
2008-03-15Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint ↵Ali Saidi
doesn't exist --HG-- extra : convert_revision : c156c49668815755c4c788f807e8eba32151aa24
2008-02-29Error out if -s is used without --caches (instead of saying you must specify aLisa Hsu
CPU). --HG-- extra : convert_revision : a3b2bfbe7e037146ac08dd08834bf255da692506
2008-02-29Configs: Make sure options don't conflictAli Saidi
--HG-- extra : convert_revision : dc9b91cf1d8e33c5e68d7faeb45dbe3e7038d14c
2008-02-28Configs: Fix some bugs we introduced in the simpoints codeAli Saidi
--HG-- extra : convert_revision : ef22c11cb3242903a484fc05dc0f96d3e5f9af72
2008-02-27Configs: Make using Simpoints easier with some config files that support ↵Rick Strong
them easily --HG-- extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
2008-02-26X86: Get PCI config space to work, and adjust address space prefix numbering ↵Gabe Black
scheme. --HG-- extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
2008-02-22add instruction count fast forwaing and max instruction optionsVilas Sridharan
--HG-- extra : convert_revision : 8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
2008-02-14Configs: Change Simulation.py to return a subclass of the CPU models rather ↵Ali Saidi
than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency. --HG-- extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
--HG-- extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ↵Gabe Black
port. --HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
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