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AgeCommit message (Expand)Author
2013-01-14config: move ruby objects under ruby_system in obj hierarchyMalek Musleh
2013-01-08config: Fix issue with changeset: a4739b6f799d.Ali Saidi
2013-01-08util: add m5_fail op.LluĂ­s Vilanova
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-12-11ruby: add support for prefetching to MESI protocolNilay Vaish
2012-12-11ruby: modify the directed tester to read/write streamsNilay Vaish
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-11-19config: Fix description of checkpoint option from cycle to tickAndreas Hansson
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-27ruby: set the is_icache param for cachesMalek Musleh
2012-10-27Ruby: Use block size in configuring directory bits in addressJason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26config: Add a check for fastmem only used with Atomic CPUAndreas Hansson
2012-10-26config: Remove unused mem_size in fs.pyAndreas Hansson
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-15ruby: improved support for functional accessesNilay Vaish
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-10-02ruby: changes to simple networkNilay Vaish
2012-09-28Configs: SE script fix for Alpha and Ruby simulationsMalek Musleh
2012-09-27Configs: Fix memtest cache latency to match new parametersAndreas Hansson
2012-09-27Configs: Fix memtest.py by moving the system portAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-12se.py Ruby: Connect TLB walker portsJoel Hestness
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-11se.py: removes error in passing options to a binaryNilay Vaish
2012-09-11Checkpoint: Pass maxtick to avoid undefined variableAndreas Hansson
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-08-21Checkpoint: Fix broken checkpointing functionalityAndreas Hansson
2012-08-16Ruby: Add RubySystem parameter to MemoryControlJason Power
2012-08-15configs: add option for repeatedly switching back-and-forth between cpu types.Anthony Gutierrez
2012-08-10Ruby: Clean up topology changesJason Power
2012-08-06Simulation.py: move code related to checkpointing to functionsNilay Vaish
2012-08-06Config: change how cpu class is setNilay Vaish
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-06-11configs: add run scripts for ics/gb versions of android and bbenchAnthony Gutierrez
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson