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Author
2013-03-28
x86: create space in bios memory map
Nilay Vaish
2013-03-22
config: return exit event instead of cause
Nilay Vaish
2013-03-22
ruby: convert Topology to regular class
Nilay Vaish
2013-03-22
ruby: network: move routers from topology to network
Nilay Vaish
2013-03-06
ruby: remove the functional copy of memory in se mode
Nilay Vaish
2013-03-06
ruby: garnet: fixed: implement functional access
Nilay Vaish
2013-02-20
config: Fix --prog-interval command line option
Ali Saidi
2013-02-15
options: add command line option for dtb file
Anthony Gutierrez
2013-02-15
config: Remove O3 dependencies
Andreas Sandberg
2013-02-15
config: Move CPU handover logic to m5.switchCpus()
Andreas Sandberg
2013-02-15
config: Cleanup CPU configuration
Andreas Sandberg
2013-02-15
cpu: Add CPU metadata om the Python classes
Andreas Sandberg
2013-02-10
config: Don't call sys.exit in interactive mode in run()
Andreas Sandberg
2013-01-31
mem: Add DDR3 and LPDDR2 DRAM controller configurations
Andreas Hansson
2013-01-24
branch predictor: move out of o3 and inorder cpus
Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-14
config: move ruby objects under ruby_system in obj hierarchy
Malek Musleh
2013-01-08
config: Fix issue with changeset: a4739b6f799d.
Ali Saidi
2013-01-08
util: add m5_fail op.
LluĂs Vilanova
2013-01-07
cpu: Rename defer_registration->switched_out
Andreas Sandberg
2013-01-07
config: Do not use hardcoded physmem in fs script
Andreas Hansson
2013-01-07
arch: Make the ISA class inherit from SimObject
Andreas Sandberg
2012-12-11
ruby: add support for prefetching to MESI protocol
Nilay Vaish
2012-12-11
ruby: modify the directed tester to read/write streams
Nilay Vaish
2012-12-06
TournamentBP: Fix some bugs with table sizes and counters
Erik Tomusk
2012-11-19
config: Fix description of checkpoint option from cycle to tick
Andreas Hansson
2012-11-02
python: Rename doDrain()->drain() and make it do the right thing
Andreas Sandberg
2012-11-02
Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Andreas Sandberg
2012-10-30
config: Unify caches used in regressions and adjust L2 MSHRs
Andreas Hansson
2012-10-27
ruby: set the is_icache param for caches
Malek Musleh
2012-10-27
Ruby: Use block size in configuring directory bits in address
Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26
config: Add a check for fastmem only used with Atomic CPU
Andreas Hansson
2012-10-26
config: Remove unused mem_size in fs.py
Andreas Hansson
2012-10-26
config: Fix the cache class naming in regression scripts
Andreas Hansson
2012-10-25
config: Use SimpleDRAM in full-system, and with o3 and inorder
Andreas Hansson
2012-10-25
config: Use shared cache config for regressions
Andreas Hansson
2012-10-15
ruby: improved support for functional accesses
Nilay Vaish
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-10-15
Regression: Use CPU clock and 32-byte width for L1-L2 bus
Andreas Hansson
2012-10-02
ruby: changes to simple network
Nilay Vaish
2012-09-28
Configs: SE script fix for Alpha and Ruby simulations
Malek Musleh
2012-09-27
Configs: Fix memtest cache latency to match new parameters
Andreas Hansson
2012-09-27
Configs: Fix memtest.py by moving the system port
Andreas Hansson
2012-09-25
Cache: add a response latency to the caches
Mrinmoy Ghosh
2012-09-19
AddrRange: Simplify AddrRange params Python hierarchy
Andreas Hansson
2012-09-12
se.py Ruby: Connect TLB walker ports
Joel Hestness
2012-09-12
Standard Switch: Drain the system before switching CPUs
Joel Hestness
2012-09-11
se.py: removes error in passing options to a binary
Nilay Vaish
2012-09-11
Checkpoint: Pass maxtick to avoid undefined variable
Andreas Hansson
2012-09-09
se.py: support specifying multiple programs via command line
Nilay Vaish
2012-08-22
Bridge: Remove NACKs in the bridge and unify with packet queue
Andreas Hansson
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