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AgeCommit message (Expand)Author
2018-02-05config: remove dead code in fs.pyNayan Deshmukh
2018-01-29config, arm: enable device tree autogeneration for bigLITTLECurtis Dunham
2018-01-29config: Embed Device Tree generation in fs.py configGlenn Bergmans
2018-01-10configs: Fill in the cpu.isa field in etrace_replay.py since no default are p...Chen Zou
2018-01-08gpu-compute: call createThreads() on cpu objs in apu_se.pyTony Gutierrez
2018-01-02config: Handle NULL simobject parameters in read_config.py.Gabe Black
2018-01-02config: Fix parsing AddrRange parameters in read_config.py.Gabe Black
2018-01-02config: Add a --checkpoint-dir argument to read_config.py.Gabe Black
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
2017-12-05config, mem, hmc: fix HMC test scriptÉder F. Zulian
2017-12-05learning_gem5: Adding code for SimpleCacheJason Lowe-Power
2017-12-05learning_gem5: Adds the simple MemObject codeJason Lowe-Power
2017-12-05learning_gem5: Add code for hello-goodbye exampleJason Lowe-Power
2017-12-05learning_gem5: Add code for simple SimObjectJason Lowe-Power
2017-11-16tests: Add tests for DRAM low power modesRadhika Jagtap
2017-11-16config: Add low power sweep for DRAMRadhika Jagtap
2017-11-13config: Fix the "script" SysPath functor.Gabe Black
2017-10-31config: Rework the SysPaths functions into functors.Gabe Black
2017-08-03configs, arm: Fix incorrect use of mem_range in bL exampleAndreas Sandberg
2017-08-03arm, config: Fix CPU names in ARM example configsAndreas Sandberg
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
2017-07-28config: Discover CPU timing models based on target ISAAndreas Sandberg
2017-07-27config, arm: SE configuration for the ARM starter kitGabor Dozsa
2017-07-27config, arm: FS configuration for the ARM starter kitGabor Dozsa
2017-07-27config, arm: Add a high-performance in order timing modelAshkan Tousi
2017-07-27config: Change mem_range attribute naming in ARM SimpleSystemGabor Dozsa
2017-07-25configs,sim-se: fix se.py multi-cpu multi-cmd issuePau Cabre
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-04config, arm: Don't import timing models for missing CPUsAndreas Sandberg
2017-07-03config: Clean up core timing model discoveryAndreas Sandberg
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
2017-07-03config: Make ex5_*.py independent of old configsAndreas Sandberg
2017-06-30config: Add missing import of 'fatal' in CpuConfigAndreas Sandberg
2017-06-30config: Make some MemConfig options optionalAndreas Sandberg
2017-06-19configs, arm: add option to enable security extensionsGedare Bloom
2017-06-15configs: fixed SimpleOpts missing error by adding library pathZhang Zheng
2017-06-13config: Warn not fail for ARM systems configured with rubyNikos Nikoleris
2017-06-13ruby, arm: Forward invalidations to the local exclusive monitorNikos Nikoleris
2017-06-13ruby: Add support for address ranges in the directoryNikos Nikoleris
2017-05-18configs: fix cpu names in big.LITTLE examplePierre-Yves Péneau
2017-05-18arm, config: added support for ex5 model of big.LITTLEPierre-Yves Péneau
2017-05-17config: Changes to boot Android NWeiping Liao
2017-05-09config: Fix up some configs to not use CPU aliases.Gabe Black
2017-05-06config: Remove support for CPU aliases.Gabe Black
2017-04-11config, arm: Add an example power modelAndreas Sandberg
2017-04-05config: Add a default system disk image for SPARC FS.Gabe Black
2017-04-03config, arm: Add multi-core KVM support to bL configAndreas Sandberg
2017-04-03config, arm: Unify checkpoint path handling in bL configsAndreas Sandberg
2017-03-01config: exit with fatal() if errorPierre-Yves Péneau