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2019-03-06invisispec-1.0 configsIru Cai
2018-02-05config: remove dead code in fs.pyNayan Deshmukh
We have not added the --generate-dtb option for non-ARM systems and hence this case becomes dead code. It also leads to error on non-ARM systems as is tries to access a non existent field. Change-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5 Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/7801 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-29config, arm: enable device tree autogeneration for bigLITTLECurtis Dunham
Change-Id: Iaa5eeb3504b3ff9e46b6f592a06d6b833c830d83 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5969 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29config: Embed Device Tree generation in fs.py configGlenn Bergmans
Equips the fs.py config routine with an extra commandline option --generate-dtb that will generate a dtb file automatically before running the simulation. Only works with ARM systems and gives a warning if the simulated system is not of --machine-type VExpress_GEM5_V1. Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5968 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10configs: Fill in the cpu.isa field in etrace_replay.py since no default are ↵Chen Zou
provided now Change-Id: I5f337b9969820bd74ed67e576e2d1a8e4666ecdb Reviewed-on: https://gem5-review.googlesource.com/7021 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-08gpu-compute: call createThreads() on cpu objs in apu_se.pyTony Gutierrez
commit 8ad26e2688b8736f9290086bb4026cc7500429e9 cpu: Don't override ISA if provided by user removed the default ISA from the BaseCPU, and instead relies on createThreads() to initiate a default ISA if none is specified. the apu_se.py script, however does not call creatThreads() leading to a fatal when constructing CPU objects. this patch adds the appropriate calls to createThreads() inside apu_se.py. Change-Id: I16a5929454c59d68a3f1b7b3858c48a70cb76412 Reviewed-on: https://gem5-review.googlesource.com/7101 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-01-02config: Handle NULL simobject parameters in read_config.py.Gabe Black
Change-Id: If0f87e8ee37099be4d0f3567db4fc34f8467e409 Reviewed-on: https://gem5-review.googlesource.com/6943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-02config: Fix parsing AddrRange parameters in read_config.py.Gabe Black
The format of AddrRange parameters was changed, but config/example/read_config.py wasn't updated for the new format. Change-Id: Ie0da7aaa47c827bacc2b4f7f44929efd868b8794 Reviewed-on: https://gem5-review.googlesource.com/6942 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-02config: Add a --checkpoint-dir argument to read_config.py.Gabe Black
This argument lets the user restore a checkpoint after loading simulator state from config.ini. Change-Id: I6e0630d75b798a1d2536e2408660843f57f46c4b Reviewed-on: https://gem5-review.googlesource.com/6941 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet. Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
Since BaseCPU.createThreads() no longer overrides the BaseCPU.isa parameter, switch_cpus should have the ISA copied. This fixes a fatal error in BaseCPU when restoring from a checkpoint. Change-Id: I4fdcacb76da46bdbe1ce37dcf05c5a6a8a9e5237 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/6241 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05config, mem, hmc: fix HMC test scriptÉder F. Zulian
This patch keeps the logic behind the HMC model implementation untouched. Additional changes: - simple hello world script using HMC (SE simulation) Usage examples: ./build/ARM/gem5.opt configs/example/hmctest.py ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=same ./build/ARM/gem5.opt configs/example/hmctest.py --enable-global-monitor --enable-link-monitor --arch=mixed ./build/ARM/gem5.opt configs/example/hmc_hello.py ./build/ARM/gem5.opt configs/example/hmc_hello.py --enable-global-monitor --enable-link-monitor Change-Id: I64eb6c9abb45376b6ed72722926acddd50765394 Reviewed-on: https://gem5-review.googlesource.com/6061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-12-05learning_gem5: Adding code for SimpleCacheJason Lowe-Power
This is the rest of the code for part 2. See http://learning.gem5.org/book/part2/simplecache.html Change-Id: I5db099266a1196914656be3858fdd5fb4f8eab48 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5023 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Adds the simple MemObject codeJason Lowe-Power
Adding more code from Learning gem5 Part II See http://learning.gem5.org/book/part2/memoryobject.html Change-Id: Iaa9480c5cdbe4090364f02e81dc1d0a0ddac392a Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5022 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Add code for hello-goodbye exampleJason Lowe-Power
Adding more code from Learning gem5 Part II See http://learning.gem5.org/book/part2/parameters.html Change-Id: I9fe5655239e011c718c5cf5fd62bebcda66ea966 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5021 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05learning_gem5: Add code for simple SimObjectJason Lowe-Power
This adds code from Learning gem5 Part II. See http://learning.gem5.org/book/part2/helloobject.html Change-Id: Ic2caa07876ca57f937729c27ce29b2cd8bf2380c Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5020 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-16tests: Add tests for DRAM low power modesRadhika Jagtap
This patch adds two regression tests that execute the script in the configs dir for triggering low power mode transitions. A separate test is required for each page policy because for close-adaptive page policy the DRAM goes into the Precharge Power-down mode while for open-adaptive page policy it goes into the Activate Power-down mode. Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5726 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-16config: Add low power sweep for DRAMRadhika Jagtap
This change adds a Python script to sweep a few parameters with a goal to trigger transitions to the low power states of the DRAM controller. This script is largely based on the sweep.py but is helpful to study the impact of inter-transaction delay on the behaviour of the DRAM in addition to typical sweep params like stride size, bank utilization and read percent. An idle period is added as the last traffic generator state to target hitting self-refresh. Change-Id: I34380afffbf2de9f4e997dfe9fff5e615e077524 Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5725 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13config: Fix the "script" SysPath functor.Gabe Black
This particular functor looks in the config root, not in the path specified by M5_ROOT like binary and disk. Change-Id: Ib007c36934c65ca9f808e995a2e0c71f0b338788 Reviewed-on: https://gem5-review.googlesource.com/5641 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-31config: Rework the SysPaths functions into functors.Gabe Black
These functions were already being treated as psuedo objects and had properties assigned to them setting what their paths were. That's a bit unusual and made it less obvious what the code was doing, but also forced the "system" function to know what all the possible path searching functions were so that they'd have their "path" property initialized properly in a central location. This change introduces a PathSearcFunc class which encapsulates the mechanisms of the old code and makes it implicitly extensible so that other path searching functions which might look in other directories can be added in other places. Change-Id: I7be28e51481a06ec83997677af99927709b18003 Reviewed-on: https://gem5-review.googlesource.com/5341 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-03configs, arm: Fix incorrect use of mem_range in bL exampleAndreas Sandberg
The change "config: Change mem_range attribute naming in ARM SimpleSystem" modified the SimpleSystem class to be compatible with the MemConfig utility script. While doing so, the way we report the memory ranges supported by the system changed, which broke the bL example configration. This changeset introduces the necessary changes to make the script work again. Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-03arm, config: Fix CPU names in ARM example configsAndreas Sandberg
The ARM example configs used to rely on CPU aliases for the AtomicSimpleCPU and KVM when configuring clusters. This broken when support for CPU aliases was removed ('config: Remove support for CPU aliases.'). This change updates the config scripts to use the full class names instead. Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4360 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
Old ARM systems used to pass the machine type in the ATAGS list passed to the kernel. This has been largely deprecated by the introduction of device trees. Switch to the DTOnly machine type by default in gem5 since all new platforms and kernel will require this behavior. Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4260 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-28config: Discover CPU timing models based on target ISAAndreas Sandberg
The CpuConfig helper currently assumes that all timing models live in the cores.arm package. This ignores the potential mismatch between the target ISA and the ISA assumptions made by the timing models. Instead of unconditionally listing all CPU models in cores.arm, list timing models from cores.generic and cores.${TARGET_ISA}. This ensures that the listed timing models support the ISA that gem5 is targeting. Change-Id: If6235af2118889638f56ac4151003f38edfe9485 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3947 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: SE configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4203 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: FS configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4202 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: Add a high-performance in order timing modelAshkan Tousi
The High-Performance In-order (HPI) CPU timing model is tuned to be representative of a modern in-order ARMv8-A implementation. The HPI core and its supporting simulation scripts, namely starter_se.py and starter_fs.py (under /configs/example/arm/) are part of the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22 Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config: Change mem_range attribute naming in ARM SimpleSystemGabor Dozsa
MemConfig.config() expects memory ranges to be defined in a particular way. This patch changes the naming of the mem_range attribute in SympleSystem to enable use of MemConfig for configuring the memory. Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4200 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-25configs,sim-se: fix se.py multi-cpu multi-cmd issuePau Cabre
Assign different pids to the different commands specified with the "--cmd" flag to configs/example/se.py Without this change, the following command line triggers a "fatal: _pid 100 is already used" error: command=$PWD/tests/test-progs/hello/bin/arm/linux/hello ./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command" Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4160 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-07-04config, arm: Don't import timing models for missing CPUsAndreas Sandberg
When importing the cores.arm package, we currently throw an exception if a timing model can't be imported due to a missing dependency (e.g., the required CPU model wasn't included in the build). This is undesirable since it prevents other, working, timing models from being added to the package. Wrap the import_module call in a try-except block and skip timing models that have missing dependencies. Change-Id: I92bab62c989f433a8a4a7bf59207d9d81b3d19e1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3946 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Clean up core timing model discoveryAndreas Sandberg
Instead of hard-coding timing models in CpuConfig.py, use introspection to find them in the cores.arm model package. Change-Id: I6642dc9cbc3f5beeeec748e716c9426c233d51ea Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3944 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Make ex5_*.py independent of old configsAndreas Sandberg
The ex5_LITTLE and ex5_big configs currently depend on Caches.py and O3_ARM_v7a.py. These aren't actual dependencies since all of the params from the caches and the old O3 model are overridden. This changeset updates the ex5 models to derive from the base SimObjects instead. Change-Id: I999e73bb9cc21ad96865c1bc0dd5973faa48ab61 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3942 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-30config: Add missing import of 'fatal' in CpuConfigAndreas Sandberg
Change-Id: I7762d344cb964c3e010135ff928c6ea12538912c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3941 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-30config: Make some MemConfig options optionalAndreas Sandberg
MemConfig currently assumes that all callers include the its full set of options in the command line parser. This is unnecessary and sometimes confusing. Make most of the options optional to avoid having to add all of them to example scripts. Change-Id: I2d73be2454427b00db16716edcfd96a47133c888 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3940 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-19configs, arm: add option to enable security extensionsGedare Bloom
Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3264 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-15configs: fixed SimpleOpts missing error by adding library pathZhang Zheng
Change-Id: I0de761c8a322a506e436d5c7f12ee509535f52fd Reviewed-on: https://gem5-review.googlesource.com/2801 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-13config: Warn not fail for ARM systems configured with rubyNikos Nikoleris
Ruby for ARM systems is not fully supported but certain configurations are expected to work. This change removes the more general fail statement and warns or fails depending on the particular configuration. Change-Id: Ic24799aff966ba15858b93482e0f24a8672d9483 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2905 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-06-13ruby, arm: Forward invalidations to the local exclusive monitorNikos Nikoleris
ARM systems require local exclusive monitors for the implementation of synchronization primitives between processors. A ruby memory system needs to forward invalidations to the local exclusive monitors to to correctly determine their state. Change-Id: I7bc4d0f2a5be0f4e36a25c87aa4a81a3f086fb3c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2904 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-13ruby: Add support for address ranges in the directoryNikos Nikoleris
Previously the directory covered a flat address range that always started from address 0. This change adds a vector of address ranges with interleaving and hashing that each directory keeps track of and the necessary flexibility to support systems with non continuous memory ranges. Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2903 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-18configs: fix cpu names in big.LITTLE examplePierre-Yves Péneau
CPU aliases have been dropped, this change fixes the big.LITTLE example. Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247 Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/3300 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-18arm, config: added support for ex5 model of big.LITTLEPierre-Yves Péneau
This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-17config: Changes to boot Android NWeiping Liao
necessary kernel command line options in FSConfig.py Change-Id: Id66f640b6beb4efa9c23080c3d2516eda688c72d Reviewed-on: https://gem5-review.googlesource.com/3320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09config: Fix up some configs to not use CPU aliases.Gabe Black
Support for CPU aliases were removed recently. Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f Reviewed-on: https://gem5-review.googlesource.com/3100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-06config: Remove support for CPU aliases.Gabe Black
This was added for backwards compatability, but it adds a decent amount of complexity. The table below shows what CPU class name to use in place of a given alias. +==========+========================================================+ | Alias | CPU class | +==========+========================================================+ | timing | TimingSimpleCPU | | atomic | AtomicSimpleCPU | | minor | MinorCPU | | detailed | DrivO3CPU | | kvm | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch | | trace | TraceCPU | +==========+========================================================+ Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08 Reviewed-on: https://gem5-review.googlesource.com/2940 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-11config, arm: Add an example power modelAndreas Sandberg
Add a script to demonstrate how power models can be wired to gem5 models. The script is meant as an example only and does not correlate with any realistic implementation. Change-Id: Ib95a74b2cb4af77a7816e3e8e89c89f3460775a1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2721 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05config: Add a default system disk image for SPARC FS.Gabe Black
When the change below removed the hard coded disk name for the SPARC FS configuration, it broke the regression which had not specified a disk name. This change adds a default disk name so that the regression will continue to work like it used to, but preserving the effect of this other change. commit 86a25bbcee88f6e69299867b6264885d738f636e Author: Jakub Jermar <jakub@jermar.eu> Date: Tue Jul 19 09:52:46 2016 -0500 config: Allow SPARC FS image to be specified on the command line Change-Id: Ieb317b2bf573a4f2fc435d34cccd1f246c28d84c Reviewed-on: https://gem5-review.googlesource.com/2645 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03config, arm: Add multi-core KVM support to bL configAndreas Sandberg
Add support for KVM in the big.LITTLE(tm) example configuration. This replaces the --atomic option with a --cpu-type option that can be used to switch between atomic, kvm, and timing simulation. When running in KVM mode, the simulation script automatically assigns separate event queues (threads) to each of the simulated CPUs. All simulated devices, including CPU child devices (e.g., interrupt controllers and caches), are assigned to event queue 0. Change-Id: Ic9a3f564db91f5a3d3cb754c5a02fdd5c17d5fdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2561 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03config, arm: Unify checkpoint path handling in bL configsAndreas Sandberg
The vanilla bL configuration file and the dist-gem5 configuration file use slightly different code paths when restoring from checkpoints. Unify this by passing the parsed options to the instantiate() method and adding an optional checkpoint keyword argument for checkpoint directories (only used by the dist-gem5 script). Change-Id: I9943ec10bd7a256465e29c8de571142ec3fbaa0e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2560 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 13:40:09 +0000