gem5 - gem5

Age	Commit message (Expand)	Author
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-03-01	Config: make option ruby available always	Nilay Vaish
2012-02-26	Make the IO bridge accept address headed to all the local APICs.	Gabe Black
2012-02-14	MEM: Fix residual bus ports and make them master/slave	Andreas Hansson
2012-02-14	Script: Fix the scripts that use the num_cpus cache parameter	Andreas Hansson
2012-02-14	MEM: Fix master/slave ports in Ruby and non-regression scripts	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	configs: fix minor config bugs posted on the mailing list	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-02-05	X86: Rename the bridge which allows commnication back to the local APICs.	Gabe Black
2012-02-01	configs: More fixes for the memory system updates	Ali Saidi
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	Ruby: Connect system port in Ruby network test	Andreas Hansson
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-28	Config: Enable O3 CPU and Ruby in FS mode	Nilay Vaish
2012-01-28	SE/FS: Get rid of FULL_SYSTEM in the configs directory	Gabe Black
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2012-01-26	configs: actually add ARMv7a-like cpu/cache file	Ronald Dreslinski
2012-01-26	configs: A more realistic configuration of an ARM-like processor	Ronald Dreslinski
2012-01-25	MEM: Fix fs.py by specifying the range size rather than end	Andreas Hansson
2012-01-23	Config: Enable using O3 CPU and Ruby in SE mode	Nilay Vaish
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2012-01-17	MEM: Make the bus bridge unidirectional and fixed address range	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-11	Ruby: Use map option for selecting b/w sparse and memory vector	Nilay Vaish
2012-01-11	Config: Add support for restoring using a timing CPU	Nilay Vaish
2012-01-10	Ruby: remove the files related to the tracer	Nilay Vaish
2012-01-10	Config: Remove short option string for cpu type	Nilay Vaish
2012-01-09	ARM: Add support for running multiple systems	Ali Saidi
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-09	cpu2000: Add missing art benchmark to all	Ali Saidi
2012-01-07	Ruby Cache: Add param for marking caches as instruction only	Nilay Vaish
2012-01-05	Config: Add an option of type 'choice' for cpu type	Nilay Vaish
2011-12-15	ARM: Update config files for Android/BBench images available on website.	Anthony Gutierrez
2011-12-01	config: command line option to specify ruby output file	gloh
2011-12-01	VNC: Add support for capturing frame buffer to file each time it is changed.	Chris Emmons
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-11-04	GARNET: adding a fault model for resilient on-chip network research.	Tushar Krishna
2011-10-29	Ruby FS: Add the options for kernel and simulation script	Nilay Vaish
2011-10-19	ARM: Fix small bug in config script that prevents android from booting	Ali Saidi
2011-08-19	ARM: Add some MP regressions and clean up the disk images and kernels a bit	Ali Saidi
2011-08-19	ARM: Add VExpress_E support with PCIe to gem5	Ali Saidi
2011-08-19	ARM: Add support for Versatile Express boards	Ali Saidi
2011-08-02	Scons: Drop RUBY as compile time option.	Nilay Vaish
2011-07-26	Ruby: Fix instantiations of DMA controller and sequencer	Nilay Vaish
2011-07-25	Ruby: Fix dma controller configs/ruby/MI_example.py	Nilay Vaish