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2017-08-03configs, arm: Fix incorrect use of mem_range in bL exampleAndreas Sandberg
The change "config: Change mem_range attribute naming in ARM SimpleSystem" modified the SimpleSystem class to be compatible with the MemConfig utility script. While doing so, the way we report the memory ranges supported by the system changed, which broke the bL example configration. This changeset introduces the necessary changes to make the script work again. Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-03arm, config: Fix CPU names in ARM example configsAndreas Sandberg
The ARM example configs used to rely on CPU aliases for the AtomicSimpleCPU and KVM when configuring clusters. This broken when support for CPU aliases was removed ('config: Remove support for CPU aliases.'). This change updates the config scripts to use the full class names instead. Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4360 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
Old ARM systems used to pass the machine type in the ATAGS list passed to the kernel. This has been largely deprecated by the introduction of device trees. Switch to the DTOnly machine type by default in gem5 since all new platforms and kernel will require this behavior. Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4260 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-28config: Discover CPU timing models based on target ISAAndreas Sandberg
The CpuConfig helper currently assumes that all timing models live in the cores.arm package. This ignores the potential mismatch between the target ISA and the ISA assumptions made by the timing models. Instead of unconditionally listing all CPU models in cores.arm, list timing models from cores.generic and cores.${TARGET_ISA}. This ensures that the listed timing models support the ISA that gem5 is targeting. Change-Id: If6235af2118889638f56ac4151003f38edfe9485 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3947 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: SE configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ia32a28eb713ba7050d790327ba6dbb73ec33b53a Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4203 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: FS configuration for the ARM starter kitGabor Dozsa
Add a full system example configuration for the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: Ifa40419d21923a32bb383d58466e421fe4260ddd Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> [ Minor cleanups and more documentation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4202 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config, arm: Add a high-performance in order timing modelAshkan Tousi
The High-Performance In-order (HPI) CPU timing model is tuned to be representative of a modern in-order ARMv8-A implementation. The HPI core and its supporting simulation scripts, namely starter_se.py and starter_fs.py (under /configs/example/arm/) are part of the ARM Research Starter Kit on System Modeling. More information can be found at: http://www.arm.com/ResearchEnablement/SystemModeling Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22 Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-27config: Change mem_range attribute naming in ARM SimpleSystemGabor Dozsa
MemConfig.config() expects memory ranges to be defined in a particular way. This patch changes the naming of the mem_range attribute in SympleSystem to enable use of MemConfig for configuring the memory. Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4200 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-25configs,sim-se: fix se.py multi-cpu multi-cmd issuePau Cabre
Assign different pids to the different commands specified with the "--cmd" flag to configs/example/se.py Without this change, the following command line triggers a "fatal: _pid 100 is already used" error: command=$PWD/tests/test-progs/hello/bin/arm/linux/hello ./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command" Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4160 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-07-04config, arm: Don't import timing models for missing CPUsAndreas Sandberg
When importing the cores.arm package, we currently throw an exception if a timing model can't be imported due to a missing dependency (e.g., the required CPU model wasn't included in the build). This is undesirable since it prevents other, working, timing models from being added to the package. Wrap the import_module call in a try-except block and skip timing models that have missing dependencies. Change-Id: I92bab62c989f433a8a4a7bf59207d9d81b3d19e1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3946 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Clean up core timing model discoveryAndreas Sandberg
Instead of hard-coding timing models in CpuConfig.py, use introspection to find them in the cores.arm model package. Change-Id: I6642dc9cbc3f5beeeec748e716c9426c233d51ea Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3944 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Make ex5_*.py independent of old configsAndreas Sandberg
The ex5_LITTLE and ex5_big configs currently depend on Caches.py and O3_ARM_v7a.py. These aren't actual dependencies since all of the params from the caches and the old O3 model are overridden. This changeset updates the ex5 models to derive from the base SimObjects instead. Change-Id: I999e73bb9cc21ad96865c1bc0dd5973faa48ab61 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3942 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-30config: Add missing import of 'fatal' in CpuConfigAndreas Sandberg
Change-Id: I7762d344cb964c3e010135ff928c6ea12538912c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3941 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-30config: Make some MemConfig options optionalAndreas Sandberg
MemConfig currently assumes that all callers include the its full set of options in the command line parser. This is unnecessary and sometimes confusing. Make most of the options optional to avoid having to add all of them to example scripts. Change-Id: I2d73be2454427b00db16716edcfd96a47133c888 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3940 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-19configs, arm: add option to enable security extensionsGedare Bloom
Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3264 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-15configs: fixed SimpleOpts missing error by adding library pathZhang Zheng
Change-Id: I0de761c8a322a506e436d5c7f12ee509535f52fd Reviewed-on: https://gem5-review.googlesource.com/2801 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-13config: Warn not fail for ARM systems configured with rubyNikos Nikoleris
Ruby for ARM systems is not fully supported but certain configurations are expected to work. This change removes the more general fail statement and warns or fails depending on the particular configuration. Change-Id: Ic24799aff966ba15858b93482e0f24a8672d9483 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2905 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-06-13ruby, arm: Forward invalidations to the local exclusive monitorNikos Nikoleris
ARM systems require local exclusive monitors for the implementation of synchronization primitives between processors. A ruby memory system needs to forward invalidations to the local exclusive monitors to to correctly determine their state. Change-Id: I7bc4d0f2a5be0f4e36a25c87aa4a81a3f086fb3c Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2904 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-13ruby: Add support for address ranges in the directoryNikos Nikoleris
Previously the directory covered a flat address range that always started from address 0. This change adds a vector of address ranges with interleaving and hashing that each directory keeps track of and the necessary flexibility to support systems with non continuous memory ranges. Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2903 Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-18configs: fix cpu names in big.LITTLE examplePierre-Yves Péneau
CPU aliases have been dropped, this change fixes the big.LITTLE example. Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247 Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/3300 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-18arm, config: added support for ex5 model of big.LITTLEPierre-Yves Péneau
This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-17config: Changes to boot Android NWeiping Liao
necessary kernel command line options in FSConfig.py Change-Id: Id66f640b6beb4efa9c23080c3d2516eda688c72d Reviewed-on: https://gem5-review.googlesource.com/3320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09config: Fix up some configs to not use CPU aliases.Gabe Black
Support for CPU aliases were removed recently. Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f Reviewed-on: https://gem5-review.googlesource.com/3100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-06config: Remove support for CPU aliases.Gabe Black
This was added for backwards compatability, but it adds a decent amount of complexity. The table below shows what CPU class name to use in place of a given alias. +==========+========================================================+ | Alias | CPU class | +==========+========================================================+ | timing | TimingSimpleCPU | | atomic | AtomicSimpleCPU | | minor | MinorCPU | | detailed | DrivO3CPU | | kvm | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch | | trace | TraceCPU | +==========+========================================================+ Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08 Reviewed-on: https://gem5-review.googlesource.com/2940 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-11config, arm: Add an example power modelAndreas Sandberg
Add a script to demonstrate how power models can be wired to gem5 models. The script is meant as an example only and does not correlate with any realistic implementation. Change-Id: Ib95a74b2cb4af77a7816e3e8e89c89f3460775a1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2721 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05config: Add a default system disk image for SPARC FS.Gabe Black
When the change below removed the hard coded disk name for the SPARC FS configuration, it broke the regression which had not specified a disk name. This change adds a default disk name so that the regression will continue to work like it used to, but preserving the effect of this other change. commit 86a25bbcee88f6e69299867b6264885d738f636e Author: Jakub Jermar <jakub@jermar.eu> Date: Tue Jul 19 09:52:46 2016 -0500 config: Allow SPARC FS image to be specified on the command line Change-Id: Ieb317b2bf573a4f2fc435d34cccd1f246c28d84c Reviewed-on: https://gem5-review.googlesource.com/2645 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03config, arm: Add multi-core KVM support to bL configAndreas Sandberg
Add support for KVM in the big.LITTLE(tm) example configuration. This replaces the --atomic option with a --cpu-type option that can be used to switch between atomic, kvm, and timing simulation. When running in KVM mode, the simulation script automatically assigns separate event queues (threads) to each of the simulated CPUs. All simulated devices, including CPU child devices (e.g., interrupt controllers and caches), are assigned to event queue 0. Change-Id: Ic9a3f564db91f5a3d3cb754c5a02fdd5c17d5fdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2561 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03config, arm: Unify checkpoint path handling in bL configsAndreas Sandberg
The vanilla bL configuration file and the dist-gem5 configuration file use slightly different code paths when restoring from checkpoints. Unify this by passing the parsed options to the instantiate() method and adding an optional checkpoint keyword argument for checkpoint directories (only used by the dist-gem5 script). Change-Id: I9943ec10bd7a256465e29c8de571142ec3fbaa0e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2560 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-03-01config: exit with fatal() if errorPierre-Yves Péneau
If output redirection is activated, the error message is printed in simout. This change ensure it will be printed in simerr. Change-Id: Ie661ac6b6978bf2e4aaaccdf23134795d764d459 Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2221 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
2017-02-14arm,config: Add dist-gem5 support to the big.LITTLE(tm) configGabor Dozsa
This patch extends the example big.LITTLE configuration to enable dist-gem5 simulations of big.LITTLE systems. Change-Id: I49c095ab3c737b6a082f7c6f15f514c269217756 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-14config: Refactor the network switch configuration fileGabor Dozsa
This patch prevents the body of the script getting executed when the script is imported as a module. Change-Id: I70a50f6295f1e7a088398017f5fa9d06fe90476a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-14arm,config: Refactor the example big.LITTLE(tm) configurationGabor Dozsa
This patch prepares future extensions and customisation of the example big.LITTLE configuration script. It breaks out the major phases into functions so they can be called from other python scripts. Change-Id: I2cb7c207c410fe14602cf17af7482719abba6c24 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-14sim, kvm: make KvmVM a System parameterCurtis Dunham
A KVM VM is typically a child of the System object already, but for solving future issues with configuration graph resolution, the most logical way to keep track of this object is for it to be an actual parameter of the System object. Change-Id: I965ded22203ff8667db9ca02de0042ff1c772220 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-02-14mem: Update DRAM configuration namesWendy Elsasser
Names of DRAM configurations were updated to reflect both the channel and device data width. Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH> The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width Total channel width can be calculated by n*w Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4 Updated scripts to match new naming convention. Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16 Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-02-09misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]Christian Menard
The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Restructure the existing sources in preparation of the addition of the * new Master Port. * Refractor names to allow for distinction of the slave and master port. * Replace the Makefile by a SConstruct. Testing Done: The examples provided in util/tlm (now util/tlm/examples/slave_port) still compile and run error free. Reviewed at http://reviews.gem5.org/r/3527/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2017-01-27mem: Add memory footprint probeRahul Thakur
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2017-01-09config: Fix missing include in fs.pyMatthias Jung
Bugfix for Elastic Traces This patch fixes the bug when elastic traces are used: build/ARM/gem5.opt \ configs/example/fs.py \ --cpu-type=arm_detailed \ --num-cpu=1 \ --mem-type=SimpleMemory \ --mem-size=512MB \ --mem-channels=1 \ --caches \ --elastic-trace-en \ --data-trace-file=data.proto.gz \ --inst-trace-file=inst.proto.gz \ --machine-type=VExpress_EMM \ --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \ --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \ --disk-image=linux-aarch32-ael.img NameError: global name 'CpuConfig' is not defined Signed-off by: Jason Lowe-Power <jason@lowepower.com>
2016-12-19python: Export periodicStatDumpAndreas Sandberg
Some configuration scripts need periodic stat dumps. One of the ways this can be achieved is by using the pariodicStatDump helper function. This function was previously only exported in the internal name space. Export it as a normal function in m5.stat instead. Change-Id: Ic88bf1fd33042a62ab436d5944d8ed778264ac98 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
2016-12-19sim: Remove redundant buildEnv importAndreas Sandberg
Change-Id: Id6bdbc0c988aa92b96e292cabc913e6b974f14bb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-12-15ruby: Detect garnet network-level deadlock.Jieming Yin
This patch detects garnet network deadlock by monitoring network interfaces. If a network interface continuously fails to allocate virtual channels for a message, a possible deadlock is detected.
2016-12-06arm, config: Add missing IOCache in bL configGabor Dozsa
This patch adds an IOCache to the example bigLITTLE configuration. An IOCache is required for correct DMA transfers when we have caches in the system. Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-05config: Add an option to generate a random topology in memcheckNikos Nikoleris
This change adds the option to use the memcheck with random memory hierarchies at the moment limited to a maximum depth of 3 allowing testing with uncommon topologies. Change-Id: Id2c2fe82a8175d9a67eb4cd7f3d2e2720a809b60 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-12-05config: Add whole line accesses to improve memchecker's coverageNikos Nikoleris
Change-Id: Ie1a047139e350ce7400f3a20be644eaff1e21428 Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-26dev: Add m5 op to toggle synchronization for dist-gem5.Michael LeBeane
This patch adds the ability for an application to request dist-gem5 to begin/ end synchronization using an m5 op. When toggling on sync, all nodes agree on the next sync point based on the maximum of all nodes' ticks. CPUs are suspended until the sync point to avoid sending network messages until sync has been enabled. Toggling off sync acts like a global execution barrier, where all CPUs are disabled until every node reaches the toggle off point. This avoids tricky situations such as one node hitting a toggle off followed by a toggle on before the other nodes hit the first toggle off.
2016-10-26gpu-compute: support in-order data delivery in GM pipeTony Gutierrez
this patch adds an ordered response buffer to the GM pipeline to ensure in-order data delivery. the buffer is implemented as a stl ordered map, which sorts the request in program order by using their sequence ID. when requests return to the GM pipeline they are marked as done. only the oldest request may be serviced from the ordered buffer, and only if is marked as done. the FIFO response buffers are kept and used in OoO delivery mode
2016-10-26config: Break out base options for usage with NULL ISAAndreas Hansson
This patch breaks out the most basic configuration options into a set of base options, to allow them to be used also by scripts that do not involve any ISA, and thus no actual CPUs or devices. The patch also fixes a few modules so that they can be imported in a NULL build, and avoid dragging in FSConfig every time Options is imported.
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