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AgeCommit message (Expand)Author
2008-02-14Configs: Change Simulation.py to return a subclass of the CPU models rather t...Ali Saidi
2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ...Gabe Black
2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without stan...Ali Saidi
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
2007-11-16Accidently kept hardcoded memory value in merge. Remove that and now ALPHA_FS...Korey Sewell
2007-11-16compile-time fix for setMipsOptions functionKorey Sewell
2007-11-15merge Ali's config change...Korey Sewell
2007-11-15fix MIPS headersKorey Sewell
2007-11-15add setMipsOptions function for MIPS usageKorey Sewell
2007-11-15Configs: Fix for benchmarks that don't use getopt.Ali Saidi
2007-11-15Config: Fix some errors in the splash2 config file.Ali Saidi
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-11-03Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if th...Ali Saidi
2007-10-25Checkpoints: Change Simulation.py to not go crazy if the simulation ends befo...Ali Saidi
2007-10-08Configuration: Move iocache outside of processors loop so it works for MP sys...Ali Saidi
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
2007-09-12Checkpointing: Fix directory regexAli Saidi
2007-09-12Checkpointing: Force drain/resume when switching a CPUAli Saidi
2007-09-05Configuration: Fix example script to only create one L2 if --l2cache and -nX ...Ali Saidi
2007-08-16PCI: Move PCI Configuration data into devices now that we can inherit paramet...Ali Saidi
2007-08-16Devices: Make EtherInts connect in the same way memory ports currently do.Ali Saidi
2007-08-12Regression: fix configuration for SPARC_FSAli Saidi
2007-08-08Added fastmem option.Vincentius Robby
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-03merge from headSteve Reinhardt
2007-08-02merge, no manual changesAli Saidi
2007-08-01Fix how the "cmd" parameter is set in se.py and remove hack in x86 process in...Gabe Black
2007-08-01Configuration: Update the drive systems kernel as well as the testsys kernel ...Ali Saidi
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
2007-07-15Fix problem with unset max_loads in memtest.Steve Reinhardt
2007-07-15Punt on old -n/-c memtest args.Steve Reinhardt
2007-07-15Add --force-bus option to memtest.py.Steve Reinhardt
2007-07-14New tree-based algorithm for creating more complex cache hierarchies.Steve Reinhardt
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
2007-06-27Get rid of coherence protocol object.Steve Reinhardt
2007-06-21Getting closer...Steve Reinhardt
2007-06-17Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-06-10the cmd argument is supposed to be an array of parameters, not one stringNathan Binkert
2007-06-09More realistic parametersNathan Binkert
2007-06-04fix SPARC....Ali Saidi
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-22memtest.py:Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-05-15add an l2 cache option to se example configAli Saidi
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
2007-05-14couple more bug fixes for intel nicAli Saidi
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
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