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2008-02-26X86: Get PCI config space to work, and adjust address space prefix numbering ↵Gabe Black
scheme. --HG-- extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
2008-02-22add instruction count fast forwaing and max instruction optionsVilas Sridharan
--HG-- extra : convert_revision : 8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
2008-02-14Configs: Change Simulation.py to return a subclass of the CPU models rather ↵Ali Saidi
than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency. --HG-- extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
--HG-- extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ↵Gabe Black
port. --HG-- extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without ↵Ali Saidi
standard switch and change some ifs to work with the default port since every port is now connected to something. --HG-- extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
2007-12-01X86: Move startup code to the system object to initialize a Linux system.Gabe Black
--HG-- extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
2007-11-16Accidently kept hardcoded memory value in merge. Remove that and now ↵Korey Sewell
ALPHA_FS quick regressions pass --HG-- extra : convert_revision : 12582bef9317cd102cafdea9001f45651d34851f
2007-11-16compile-time fix for setMipsOptions functionKorey Sewell
--HG-- extra : convert_revision : e008f6d314d4891cb6ddc9cbf96fbcc6eee53b35
2007-11-15merge Ali's config change...Korey Sewell
--HG-- extra : convert_revision : ada34ebc392d84f1225b4ff3e25f353396aa102f
2007-11-15fix MIPS headersKorey Sewell
--HG-- extra : convert_revision : 2870a146a1be0e8c80878090f39c0eaa15d2eb13
2007-11-15add setMipsOptions function for MIPS usageKorey Sewell
--HG-- extra : convert_revision : 42909d66a46201757cbdb14f75cccbd6b27d1f18
2007-11-15Configs: Fix for benchmarks that don't use getopt.Ali Saidi
--HG-- extra : convert_revision : 6cbc7bb360c282821dd9da7814e0ac8b689f5d01
2007-11-15Config: Fix some errors in the splash2 config file.Ali Saidi
--HG-- extra : convert_revision : 7bcb0f039e0609f95a081ef3aba2edb1ffa742f2
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-11-03Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if ↵Ali Saidi
that isn't set use cwd. --HG-- extra : convert_revision : 6548dd6de376dd59285a37a03bcf2525f8fc3845
2007-10-25Checkpoints: Change Simulation.py to not go crazy if the simulation ends ↵Ali Saidi
before the number of checkpoints requested are created. --HG-- extra : convert_revision : 865179134a219b34dbbba698e1fa0da7c452e074
2007-10-08Configuration: Move iocache outside of processors loop so it works for MP ↵Ali Saidi
systems --HG-- extra : convert_revision : 0ba563555a94eb22a6d4e402388e75e70d3556c2
2007-10-07X86: Adjust the config scripts for x86 fs.Gabe Black
--HG-- extra : convert_revision : 36ed22b50066f54be0e51c3419babc07dd218e10
2007-09-12Checkpointing: Fix directory regexAli Saidi
--HG-- extra : convert_revision : 4d3958eda66209373249e54e7deadd1a7442e828
2007-09-12Checkpointing: Force drain/resume when switching a CPUAli Saidi
--HG-- extra : convert_revision : 7d9c3f4c8c357e3a9214deba5df3581beeaf7cb6
2007-09-05Configuration: Fix example script to only create one L2 if --l2cache and -nX ↵Ali Saidi
are given as parameters. Patch submitted by: Jonas Diemer [diemer (a) ida.ing.tu-bs.de] --HG-- extra : convert_revision : 1dfc548d2bc33d622d829bbf385f4bf9700711cd
2007-08-16PCI: Move PCI Configuration data into devices now that we can inherit ↵Ali Saidi
parameters. --HG-- extra : convert_revision : bd2214b28fb46a9a9e9e204e0539be33acb548ad
2007-08-16Devices: Make EtherInts connect in the same way memory ports currently do.Ali Saidi
--HG-- extra : convert_revision : 765b096785a77df9adc4791c9101b90696bd7be2
2007-08-12Regression: fix configuration for SPARC_FSAli Saidi
--HG-- extra : convert_revision : 88aa9649cc1b4d8165616e98880d3d6cd2a75762
2007-08-08Added fastmem option.Vincentius Robby
Lets CPU accesses to physical memory bypass Bus. --HG-- extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-03merge from headSteve Reinhardt
--HG-- extra : convert_revision : 21f7afe2719c00744c0981212c1ee6e442238e01
2007-08-02merge, no manual changesAli Saidi
--HG-- extra : convert_revision : 8504bddf1f73a4186cebc03c3e52e42ea38361fc
2007-08-01Fix how the "cmd" parameter is set in se.py and remove hack in x86 process ↵Gabe Black
initialization code. --HG-- extra : convert_revision : 1fc741eea956ebfa4cef488eef4333d1f50617a6
2007-08-01Configuration: Update the drive systems kernel as well as the testsys kernel ↵Ali Saidi
with cmd line option. --HG-- extra : convert_revision : 5dfb0db65452c0b7aa3e2dc2a0209e3f8e23811f
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
Atomic mode seems to work. Timing is closer but not there yet. --HG-- extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-07-15Fix problem with unset max_loads in memtest.Steve Reinhardt
Also make default 0, and make that mean run forever. --HG-- extra : convert_revision : 3e60a52b1c5e334a9ef3d744cf7ee1d851ba4aa9
2007-07-15Punt on old -n/-c memtest args.Steve Reinhardt
Also added comments to document treespec format. --HG-- extra : convert_revision : fa9e8f66b68b96a4efca8a7fe6e7c37367382d9d
2007-07-15Add --force-bus option to memtest.py.Steve Reinhardt
--HG-- extra : convert_revision : 101735cca426903704ff2edaff051fa7c5bfc46c
2007-07-14New tree-based algorithm for creating more complex cache hierarchies.Steve Reinhardt
--HG-- extra : convert_revision : de8dd4ef5dae0f3e084461e8ef7c549653e61d3f
2007-06-30Get rid of remaining traces of obsolete CoherenceProtocol object.Steve Reinhardt
--HG-- extra : convert_revision : c5555b00bef1b304a84886188ad2c0dcb4d7c5b9
2007-06-27Get rid of coherence protocol object.Steve Reinhardt
--HG-- extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
2007-06-21Getting closer...Steve Reinhardt
configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. --HG-- extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-17Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 configs/example/memtest.py: Hand merge redundant changes. --HG-- extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-10the cmd argument is supposed to be an array of parameters, not one stringNathan Binkert
--HG-- extra : convert_revision : dffdaa94a1f28f3709515a9eeed420552d8c7b22
2007-06-09More realistic parametersNathan Binkert
--HG-- extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
2007-06-04fix SPARC....Ali Saidi
configs/common/FSConfig.py: fix SPARC --HG-- extra : convert_revision : 34a36c0f626f3fb8a1526ec194a9b0cdae32fed4
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-22memtest.py:Steve Reinhardt
Make clocks more reasonable. Fix bug in sense of options.timing flag. configs/example/memtest.py: Fix bug in sense of options.timing flag. configs/example/memtest.py: Make clocks more reasonable. --HG-- extra : convert_revision : 3715697988c56e92a4da129b42026d0623f5e85e
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-15add an l2 cache option to se example configAli Saidi
configs/common/Options.py: configs/example/fs.py: move l2 cache option to Options.py --HG-- extra : convert_revision : 5c0071c2827f7db6d56229d5276326364b50f0c8
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here src/mem/bridge.cc: src/mem/bridge.hh: hopefully the final hacky change to make the bus bridge work ok --HG-- extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c
2007-05-14couple more bug fixes for intel nicAli Saidi
src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: couple more bug fixes --HG-- extra : convert_revision : ae5b806528c1ec06f0091e1f6e50fc0721057ddb
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