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2015-09-16config: Add configs scripts used in Learning gem5Jason Lowe-Power
Added a new directory in configs (learning_gem5) to hold the scripts that are used in the book. See http://lowepower.com/jason/learning_gem5/ for a working copy. For now, only the scripts in Part 1: Getting started with gem5 have been added. A separate patch adds tests for these scripts. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-06config: allow ruby to be used with Minor CPUNilay Vaish
2015-09-01ruby: remove random seedNilay Vaish
We no longer use the C library based random number generator: random(). Instead we use the C++ library provided rng. So setting the random seed for the RubySystem class has no effect. Hence the variable and the corresponding option are being dropped.
2015-08-30ruby: specify number of vnets for each protocolNilay Vaish
The default value for number of virtual networks is being removed. Each protocol should now specify the value it needs.
2015-08-21mem: Add explicit Cache subclass and make BaseCache abstractAndreas Hansson
Open up for other subclasses to BaseCache and transition to using the explicit Cache subclass. --HG-- rename : src/mem/cache/BaseCache.py => src/mem/cache/Cache.py
2015-08-21ruby: Move Rubys cache class from Cache.py to RubyCache.pyAndreas Hansson
This patch serves to avoid name clashes with the classic cache. For some reason having two 'SimObject' files with the same name creates problems. --HG-- rename : src/mem/ruby/structures/Cache.py => src/mem/ruby/structures/RubyCache.py
2015-08-19ruby: reverts to changeset: bf82f1f7b040Nilay Vaish
2015-08-14ruby: profiler: provide the number of vnets through ruby systemNilay Vaish
The aim is to ultimately do away with the static function Network::getNumberOfVirtualNetworks().
2015-08-14ruby: remove random seedNilay Vaish
We no longer use the C library based random number generator: random(). Instead we use the C++ library provided rng. So setting the random seed for the RubySystem class has no effect. Hence the variable and the corresponding option are being dropped.
2015-08-14ruby: Protocol changes for SimObject MessageBuffersJoel Hestness
2015-08-14ruby: Expose MessageBuffers as SimObjectsJoel Hestness
Expose MessageBuffers from SLICC controllers as SimObjects that can be manipulated in Python. This patch has numerous benefits: 1) First and foremost, it exposes MessageBuffers as SimObjects that can be manipulated in Python code. This allows parameters to be set and checked in Python code to avoid obfuscating parameters within protocol files. Further, now as SimObjects, MessageBuffer parameters are printed to config output files as a way to track parameters across simulations (e.g. buffer sizes) 2) Cleans up special-case code for responseFromMemory buffers, and aligns their instantiation and use with mandatoryQueue buffers. These two special buffers are the only MessageBuffers that are exposed to components outside of SLICC controllers, and they're both slave ends of these buffers. They should be exposed outside of SLICC in the same way, and this patch does it. 3) Distinguishes buffer-specific parameters from buffer-to-network parameters. Specifically, buffer size, randomization, ordering, recycle latency, and ports are all specific to a MessageBuffer, while the virtual network ID and type are intrinsics of how the buffer is connected to network ports. The former are specified in the Python object, while the latter are specified in the controller *.sm files. Unlike buffer-specific parameters, which may need to change depending on the simulated system structure, buffer-to-network parameters can be specified statically for most or all different simulated systems.
2015-08-14ruby: Remove the RubyCache/CacheMemory latencyJoel Hestness
The RubyCache (CacheMemory) latency parameter is only used for top-level caches instantiated for Ruby coherence protocols. However, the top-level cache hit latency is assessed by the Sequencer as accesses flow through to the cache hierarchy. Further, protocol state machines should be enforcing these cache hit latencies, but RubyCaches do not expose their latency to any existng state machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter is superfluous for all caches. This is confusing for users. As a step toward pushing L0/L1 cache hit latency into the top-level cache controllers, move their latencies out of the RubyCache declarations and over to their Sequencers. Eventually, these Sequencer parameters should be exposed as parameters to the top-level cache controllers, which should assess the latency. NOTE: Assessing these latencies in the cache controllers will require modifying each to eliminate instantaneous Ruby hit callbacks in transitions that finish accesses, which is likely a large undertaking.
2015-08-03misc: Coupling gem5 with SystemC TLM2.0Matthias Jung
Transaction Level Modeling (TLM2.0) is widely used in industry for creating virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant implementation of an external gem5 port, that enables the usage of gem5 as a TLM initiator component in SystemC based virtual platforms. Both TLM coding paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are supported. Compared to the original patch a TLM memory manager was added. Furthermore, the transaction object was removed and for each TLM payload a PacketPointer that points to the original gem5 packet is added as an TLM extension. For event handling single events are now created. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-08-03ruby: correctly number the sequencer in MESI_Three_Level.pyNilay Vaish
2015-07-20config: add base class for ruby controllersDavid Hashe
The CntrlBase python class handles configuration parameters such as running counts of controllers and sequencers.
2015-07-20ruby: initialize replacement policies with their own simobjsDavid Hashe
this is in preparation for other replacement policies that take additional parameters.
2015-07-21configs: network test: remove redundant physical memoryNilay Vaish
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2015-07-04config: Update location of ruby topologies in helpDavid Hashe
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
This patch takes the final step in removing the is_top_level parameter from the cache. With the recent changes to read requests and write invalidations, the parameter is no longer needed, and consequently removed. This also means that asymmetric cache hierarchies are now fully supported (and we are actually using them already with L1 caches, but no table-walker caches, connected to a shared L2).
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
This patch adds a parameter to the BaseCache to enable a read-only cache, for example for the instruction cache, or table-walker cache (not for x86). A number of checks are put in place in the code to ensure a read-only cache does not end up with dirty data. A follow-on patch adds suitable read requests to allow a read-only cache to explicitly ask for clean data.
2015-06-01kvm, arm: Add support for aarch64Andreas Sandberg
This changeset adds support for aarch64 in kvm. The CPU module supports both checkpointing and online CPU model switching as long as no devices are simulated by the host kernel. It currently has the following limitations: * The system register based generic timer can only be simulated by the host kernel. Workaround: Use a memory mapped timer instead to simulate the timer in gem5. * Simulating devices (e.g., the generic timer) in the host kernel requires that the host kernel also simulates the GIC. * ID registers in the host and in gem5 must match for switching between simulated CPUs and KVM. This is particularly important for ID registers describing memory system capabilities (e.g., ASID size, physical address size). * Switching between a virtualized CPU and a simulated CPU is currently not supported if in-kernel device emulation is used. This could be worked around by adding support for switching to the gem5 (e.g., the KvmGic) side of the device models. A simpler workaround is to avoid in-kernel device models altogether.
2015-05-15config: Use null memory for DRAM sweep scriptAndreas Hansson
Do not waste time when we do not care about the data.
2015-05-15config: Add new MemConfig options to DRAM sweep scriptWendy Elsasser
Update script to match current MemConfig options with external_memory_system option set to 0.
2015-05-05arch, cpu: Do not forward snoops to table walkerAndreas Hansson
This patch simplifies the overall CPU by changing the TLB caches such that they do not forward snoops to the table walker port(s). Note that only ARM and X86 are affected. There is no reason for the ports to snoop as they do not actually take any action, and from a performance point of view we are better of not snooping more than we have to. Should it at a later point be required to snoop for a particular TLB design it is easy enough to add it back.
2015-04-29cpu: o3: replace issueLatency with bool pipelinedNilay Vaish
Currently, each op class has a parameter issueLat that denotes the cycles after which another op of the same class can be issued. As of now, this latency can either be one cycle (fully pipelined) or same as execution latency of the op (not at all pipelined). The fact that issueLat is a parameter of type Cycles makes one believe that it can be set to any value. To avoid the confusion, the parameter is being renamed as 'pipelined' with type boolean. If set to true, the op would execute in a fully pipelined fashion. Otherwise, it would execute in an unpipelined fashion.
2015-04-23config: enable setting SE-mode environment variables from filebpotter
2015-04-20config: Remove memory aliases and rely on class nameAndreas Hansson
Instead of maintaining two lists, rely entirely on the class name. There is really no point in causing unecessary confusion.
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
This patch ensures that the CPU progress Event is triggered for the new set of switched_cpus that get scheduled (e.g. during fast-forwarding). it also avoids printing the interval state if the cpu is currently switched out. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-08config: Support full-system with SST's memory systemCurtis Dunham
This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories.
2015-03-27arm, configs: Do not forward snoops from I cacheAndreas Hansson
This fix simply tells the I cache to not forward snoops to the fetch unit (since there is really no reason to do so).
2015-03-23config: expand '~' and '~user' in pathsSteve Reinhardt
2015-03-23config: Add ability to exit simulation after initializationCurtis Dunham
When using gem5 as a slave simulator, it will not advance the clock on its own and depends on the master simulator calling simulate(). This new option lets us use the Python scripts to do all the configuration while stopping short of actually simulating anything.
2015-03-19config: Add soak test for memtest.pyAndreas Hansson
This patch adds a random option to memtest.py which allows the user to easily test valid random tree topologies. The patch also adds a wrapper script to run soak tests using the newly introduced option. We also adjust the progress interval and progress limit check to make the output less noisy, and avoid false positives. Bring on the pain.
2015-03-19config: Specify OS type and release on command lineChris Emmons
This patch enables users to speficy --os-type on the command line. This option is used to take specific actions for an OS type, such as changing the kernel command line. This patch is part of the Android KitKat enablement.
2015-03-19config: Fix DRAM rank option in sweep scriptAndreas Hansson
Align with changes in the common bits.
2015-03-09config: Fix for 'android' lookup in disk nameRizwana Begum
This patch modifies FSConfig.py to look for 'android' only in disk image name. Before this patch, 'android' was searched in full disk path. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
Previously, the user would have to manually set access_backing_store=True on all RubyPorts (Sequencers) in the config files. Now, instead there is one global option that each RubyPort checks on initialization. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-02-16config: Add memcheck stress testAndreas Hansson
This is a rather unfortunate copy of the memtest.py example script, that actually stresses the system with true sharing as opposed to the false sharing of the MemTest. To do so it uses TrafficGen instances to generate the reads/writes, and MemCheckerMonitor combined with the MemChecker to check the validity of the read/written values. As a bonus, this script also enables the addition of prefetchers, and the traffic is created to have a mix of random addresses and linear strides. We use the TaggedPrefetcher since the packets do not have a request with a PC. At the moment the code is almost identical to the memtest.py script, and no effort has been made to factor out the construction of the tree. The challenge is that the instantiation and connection of the testers and monitors is done as part of the tree building.
2015-01-16config: add --root-device machine parameterCurtis Dunham
In case /dev/sda1 is not actually the boot partition for an image, we can override it on the command line or in a benchmark definition.
2015-02-11config: Revamp memtest to allow testers on any levelAndreas Hansson
This patch revamps the memtest example script and allows for the insertion of testers at any level in the cache hierarchy. Previously all created topologies placed testers only at the very top, and the tree was thus entirely symmetric. With the changes made, it is possible to not only place testers at the leaf caches (L1), but also to connect testers at the L2, L3 etc. As part of the changes the object hierarchy is also simplified to ensure that the visual representation from the DOT printing looks sensible. Using SubSystems to group the objects is one of the key features.
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed. The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work. In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing.
2015-02-05config: rename 'file' varSteve Reinhardt
Rename uses of 'file' as a local variable to avoid conflict with the built-in type of the same name.
2015-02-05config: make M5_PATH a real search pathSteve Reinhardt
Although you can put a list of colon-separated directory names in M5_PATH, the current code just takes the first one that exists and assumes all files must live there. This change makes the code search the specified list of directories for each individual binary or disk image that's requested. The main motivation is that the x86/Alpha binaries and the ARM binaries are in separate downloads, and thus naturally end up in separate directories. With this change, you can have M5_PATH point to those two directories, then run any FS regression test without changing M5_PATH. Currently, you either have to merge the two download directories or change M5_PATH (or do something else I haven't figured out).
2015-02-03config: Add XOR hashing to the DRAM channel interleavingAndreas Hansson
This patch uses the recently added XOR hashing capabilities for the DRAM channel interleaving. This avoids channel biasing due to strided access patterns.
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
This patch changes the DRAM channel interleaving default behaviour to be more representative. The default address mapping (RoRaBaCoCh) moves the channel bits towards the least significant bits, and uses 128 byte as the default channel interleaving granularity. These defaults can be overridden if desired, but should serve as a sensible starting point for most use-cases.
2015-01-30config: arm: fix os_flagsMalek Musleh
Fix the makeArmSystem routine to reflect recent changes that support kernel commandline option when running android. Without this fix, trying to run android encounters a 'reference before assignment' error. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-01-20config, ruby: connect dma to networkMalek Musleh
DMA Controller was not being connected to the network for the MESI_Three_Level protocol as was being done in the other protocol config files. Without this patch, this protocol segfaults during startup. Committed by: Nilay Vaish <nilay@cs.wisc.edu>