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AgeCommit message (Expand)Author
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-10-02ruby: changes to simple networkNilay Vaish
2012-09-28Configs: SE script fix for Alpha and Ruby simulationsMalek Musleh
2012-09-27Configs: Fix memtest cache latency to match new parametersAndreas Hansson
2012-09-27Configs: Fix memtest.py by moving the system portAndreas Hansson
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-12se.py Ruby: Connect TLB walker portsJoel Hestness
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-11se.py: removes error in passing options to a binaryNilay Vaish
2012-09-11Checkpoint: Pass maxtick to avoid undefined variableAndreas Hansson
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-08-21Checkpoint: Fix broken checkpointing functionalityAndreas Hansson
2012-08-16Ruby: Add RubySystem parameter to MemoryControlJason Power
2012-08-15configs: add option for repeatedly switching back-and-forth between cpu types.Anthony Gutierrez
2012-08-10Ruby: Clean up topology changesJason Power
2012-08-06Simulation.py: move code related to checkpointing to functionsNilay Vaish
2012-08-06Config: change how cpu class is setNilay Vaish
2012-07-23Config: Use clock option in se/fs script and pass to switch_cpusAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-06-11configs: add run scripts for ics/gb versions of android and bbenchAnthony Gutierrez
2012-06-07Config: call to setWorkCountOptions() for all ISAsNilay Vaish
2012-06-07Config: Remove setMipsOptionsNilay Vaish
2012-06-07Config: changes to a couple of error msgsNilay Vaish
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-05-16Config: Fix a typo in the se.py script for setting fastmemAndreas Hansson
2012-05-03Config: Fix help msg for option --mem-sizeJayneel Gandhi
2012-04-17SE Config: Changed se.py to support multithreaded modeJayneel Gandhi
2012-04-16Config: Add command line options for disk image and memory sizeJayneel Gandhi
2012-04-06ruby: set SimpleTiming as the default cpuBrad Beckmann
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-05Config: corrects the way Ruby attaches to the DMA portsNilay Vaish
2012-04-05Ruby: Fix the example configurations option parsingAndreas Hansson
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-03-28Config: Change the way options are addedNilay Vaish
2012-03-27Config: Move setWorkCountOptions() to Simulation.pyNilay Vaish
2012-03-16ruby_fs.py: Add call to createInterruptController()Nilay Vaish
2012-03-16FSConfig.py: fix a typo makeLinuxAlphaRubySystemNilay Vaish
2012-03-11se.py: Changes to ruby portion due to SE/FS mergeNilay Vaish
2012-03-09ARM: Fix memory starting at non-zero address and exceeding max mem for a system.Ali Saidi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01x86: Fix switching of CPUsNilay Vaish