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AgeCommit message (Expand)Author
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
2012-02-14MEM: Fix master/slave ports in Ruby and non-regression scriptsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12configs: fix minor config bugs posted on the mailing listAli Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-02-05X86: Rename the bridge which allows commnication back to the local APICs.Gabe Black
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-30Merge with main repository.Gabe Black
2012-01-30Ruby: Connect system port in Ruby network testAndreas Hansson
2012-01-29Yet another merge with the main repository.Gabe Black
2012-01-28Config: Enable O3 CPU and Ruby in FS modeNilay Vaish
2012-01-28SE/FS: Get rid of FULL_SYSTEM in the configs directoryGabe Black
2012-01-28SE/FS: Make SE vs. FS mode a runtime parameter.Gabe Black
2012-01-26configs: actually add ARMv7a-like cpu/cache fileRonald Dreslinski
2012-01-26configs: A more realistic configuration of an ARM-like processorRonald Dreslinski
2012-01-25MEM: Fix fs.py by specifying the range size rather than endAndreas Hansson
2012-01-23Config: Enable using O3 CPU and Ruby in SE modeNilay Vaish
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-11Ruby: Use map option for selecting b/w sparse and memory vectorNilay Vaish
2012-01-11Config: Add support for restoring using a timing CPUNilay Vaish
2012-01-10Ruby: remove the files related to the tracerNilay Vaish
2012-01-10Config: Remove short option string for cpu typeNilay Vaish
2012-01-09ARM: Add support for running multiple systemsAli Saidi
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2012-01-09cpu2000: Add missing art benchmark to allAli Saidi
2012-01-07Ruby Cache: Add param for marking caches as instruction onlyNilay Vaish
2012-01-05Config: Add an option of type 'choice' for cpu typeNilay Vaish
2011-12-15ARM: Update config files for Android/BBench images available on website.Anthony Gutierrez
2011-12-01config: command line option to specify ruby output filegloh
2011-12-01VNC: Add support for capturing frame buffer to file each time it is changed.Chris Emmons
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-11-04GARNET: adding a fault model for resilient on-chip network research.Tushar Krishna
2011-10-29Ruby FS: Add the options for kernel and simulation scriptNilay Vaish
2011-10-19ARM: Fix small bug in config script that prevents android from bootingAli Saidi
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-08-02Scons: Drop RUBY as compile time option.Nilay Vaish
2011-07-26Ruby: Fix instantiations of DMA controller and sequencerNilay Vaish
2011-07-25Ruby: Fix dma controller configs/ruby/MI_example.pyNilay Vaish
2011-07-11se.py: Fixes the way ruby's options are addedNilay Vaish
2011-07-03Network_test: Conform it with functional access changes in RubyNilay Vaish
2011-06-30config: removed unnecessary slashesBrad Beckmann
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt