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2014-04-19config: ruby: remove memory controller from network testNilay Vaish
It is not in use and not required as such.
2014-04-14arm: set default kernels for VExpress_EMM and VExpress_EMM64Anthony Gutierrez
2014-04-10config: add num-work-ids command line optionGedare Bloom
Adds the parameter --num-work-ids to Options.py and reads the parameter into the System params in Simulation.py. This parameter enables setting the number of possible work items to different than 16. Support for this parameter already exists in src/sim/System.py, so this changeset only affects the Python config files. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-01configs: use SimpleMemory when using ruby in se modeNilay Vaish
A recent changeset altered the default memory class to DRAMCtrl. In se mode, ruby uses the physical memory to check if a given address is within the bounds of the physical memory. SimpleMemory is enough for this. Moreover, SimpleMemory does not check whether it is connected or not, something which DRAMCtrl does.
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant). As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future. --HG-- rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh
2014-03-23mem: Change memory defaults to be more representativeAndreas Hansson
Make the default memory type DDR3-1600 x64, and use the open-adaptive page policy. This change is aiming to ensure that users by default are using a realistic memory system.
2014-03-23config: Add a DRAM efficiency-sweep scriptAndreas Hansson
This patch adds a configuration that simplifies evaluation of DRAM controller configurations by automating a sweep of stride size and bank parallelism. It works in a rather unconventional way, as it needs to print the traffic generator stimuli based on the memory organisation. Hence, it starts by configuring the memory, then it prints a traffic-generator config file, and loads it. The resulting stats have one period per data point, identified by the stride size, and the number of banks being used.
2014-03-23mem: More descriptive address-mapping scheme namesAndreas Hansson
This patch adds the row bits to the name of the address mapping schemes to make it more clear that all the current schemes places the row bits as the most significant bits.
2014-03-20ruby: garnet: convert network interfaces into clocked objectsNilay Vaish
This helps in configuring the network interfaces from the python script and these objects no longer rely on the network object for the timing information.
2014-03-20config: ruby: rename _cpu_ruby_ports to _cpu_portsNilay Vaish
2014-03-20config: fs.py: move creating of test/drive systems to functionsNilay Vaish
The code that creates test and drive systems is being moved to separate functions so as to make the code more readable. Ultimately the two functions would be combined so that the replicated code is eliminated.
2014-03-20config: remove ruby_fs.pyNilay Vaish
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression.
2014-03-20ruby: no piobus in se modeNilay Vaish
Piobus was recently added to se scripts for ruby so that the interrupt controller can be connected to something (required since the interrupt controller sends address range messages). This patch removes the piobus and instead, the pio port of ruby port will now ignore the range change messages in se mode.
2014-03-17config: ruby: remove piobus from protocolsNilay Vaish
This patch removes the piobus from the protocol config files. The ports are now connected to the piobus in the Ruby.py file.
2014-02-24ruby: correct errors in changeset 4eec7bdde5b0Nilay Vaish
Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch. Firstly, we create interrupt controllers in the se mode, but no piobus was being created. RubyPort, which earlier used to ignore range changes now forwards those to the piobus. The lack of piobus resulted in segmentation fault. This patch creates a piobus even in se mode. It is not created only when some tester is running. Secondly, I had missed out on modifying port connections for other coherence protocols.
2014-02-23ruby: route all packets through ruby portNilay Vaish
Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch.
2014-02-23config: topologies: slight code refactorNilay Vaish
2014-02-21config: ruby_random_test: updates due to recent unrelated changesNilay Vaish
2014-02-18arm: armv8 boot options to enable v8Anthony Gutierrez
Modifies FSConfig.py to enable ARMv8 compatibility. To boot gem5 with ARMv8: Download the v8 kernel, .dtb file, and root FS from: http://gem5.org/Download Download the ARMv8 toolchain, and add the bin dir to your path: http://www.linaro.org/engineering/engineering-projects/armv8 Build gem5 for ARM Build the v8 bootloader (in gem5/system/arm/aarch64_bootloader) Make script in gem5/system/arm/aarch64_bootloader will require v8 toolchain, drop the produced boot_emm.arm64 in $(M5_PATH)/binaries/ Run: $ build/ARM/gem5.fast configs/example/fs.py --machine-type=VExpress_EMM64 \ --kernel=/path/to/kernel/vmlinux-linaro-tracking \ --dtb-filename=/path/to/dtb/rtsm_ve-aemv8a.dtb \ --disk-image=/path/to/img/linaro-minimal-armv8.img
2014-02-18mem: Add a wrapped DRAMSim2 memory controllerAndreas Hansson
This patch adds DRAMSim2 as a memory controller by wrapping the external library and creating a sublass of AbstractMemory that bridges between the semantics of gem5 and the DRAMSim2 interface. The DRAMSim2 wrapper extracts the clock period from the config file. There is no way of extracting this information from DRAMSim2 itself, so we simply read the same config file and get it from there. To properly model the response queue, the wrapper keeps track of how many transactions are in the actual controller, and how many are stacking up waiting to be sent back as responses (in the wrapper). The latter requires us to move away from the queued port and manage the packets ourselves. This is due to DRAMSim2 not having any flow control on the response path. DRAMSim2 assumes that the transactions it is given are matching the burst size of the choosen memory. The wrapper checks to ensure the cache line size of the system matches the burst size of DRAMSim2 as there are currently no provisions to split the system requests. In theory we could allow a cache line size smaller than the burst size, but that would lead to inefficient use of the DRAM, so for not we fatal also in this case.
2014-01-31config: correct bug in x86 drive sys instantiationNilay Vaish
2014-01-28x86: add a warning about the number of memory controllersNilay Vaish
When memory size > 3GB, print a warning that twice the number of memory controllers would be created.
2014-01-27config: allow more than 3GB of memory for x86 simulationsNilay Vaish
This patch edits the configuration files so that x86 simulations can have more than 3GB of memory. It also corrects a bug in the MemConfig.py script.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2014-01-10ruby: move all statistics to stats.txt, eliminate ruby.statsNilay Vaish
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers.
2014-01-04ruby: rename MESI_CMP_directory to MESI_Two_LevelNilay Vaish
This is because the next patch introduces a three level hierarchy. --HG-- rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
2014-01-04ruby: remove cntrl_id from python config scripts.Nilay Vaish
2014-01-04ruby: some small changesNilay Vaish
2014-01-03config, x86: move kernel specification from tests to FSConfig.pySteve Reinhardt
For some reason, the default x86 kernel is specified in tests/configs/x86_generic.py and not in configs/common/FSConfig.py, where the kernels for all the other ISAs are. This means that running configs/example/fs.py for x86 fails because no kernel is specified. Moving the specification over fixes this problem. There is another problem that this uncovers, which is that going past the init stage (i.e., past where the regression test stops) fails because the fsck test on the disk device fails, but that's a separate issue.
2013-12-20ruby: mesi: remove owner and sharer fields from directory tagsNilay Vaish
The directory controller should not have the sharer field since there is only one level 2 cache. Anyway the field was not in use. The owner field was being used to track the l2 cache version (in case of distributed l2) that has the cache block under consideration. The information is not required since the version of the level 2 cache can be obtained from a subset of the address bits.
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
the current implementation of the fetch buffer in the o3 cpu is only allowed to be the size of a cache line. some architectures, e.g., ARM, have fetch buffers smaller than a cache line, see slide 22 at: http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf this patch allows the fetch buffer to be set to values smaller than a cache line.
2013-10-17util: Streamline .apc project convertsion scriptDam Sunwoo
This Python script generates an ARM DS-5 Streamline .apc project based on gem5 run. To successfully convert, the gem5 runs needs to be run with the context-switch-based stats dump option enabled (The guest kernel also needs to be patched to allow gem5 interrogate its task information.) See help for more information.
2013-10-17arm, config: Fix a small issue with the dtb file being specifiedAli Saidi
2013-10-17config: Fix memtest example scriptAli Saidi
2013-10-09config: correct example ruby scriptsNilay Vaish
A couple of recent changesets added/deleted/edited some variables that are needed for running the example ruby scripts. This changeset edits these scripts to bring them to a working state.
2013-10-07config: set cwd for processes in se.pyNilay Vaish
2013-09-30x86: Add support for m5ops through a memory mapped interfaceAndreas Sandberg
In order to support m5ops in virtualized environments, we need to use a memory mapped interface. This changeset adds support for that by reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR interface for m5ops. The mapping is done in the X86ISA::TLB::finalizePhysical() which means that it just works for all of the CPU models, including virtualized ones.
2013-09-30config: Add a 'kvm' CPU aliasAndreas Sandberg
Add a CPU alias, 'kvm', for the first available KVM-accelerated CPU model.
2013-09-17configs: Fix ruby_fs.py cache line sizeJoel Hestness
Recent changes added setting of system-wide cache line size and these settings occur in the top-level configs (se.py and fs.py). This setting also needs to take place in ruby_fs.py. This change sets the cache line size as appropriate.
2013-09-12config: Add voltage domain to Ruby example scriptsAndreas Hansson
This patch adds the minimum required voltage domain configuration to the Ruby example scripts.
2013-09-11config: Initialize and check cpt_starttickJoel Hestness
The previous changeset (9816) that fixes the use of max ticks introduced the variable cpt_starttick, which is used for setting the relative max tick. Unfortunately, with checkpointing at an instruction count or with simpoints, the checkpoint tick is not stored conveniently, so to ensure that cpt_starttick is initialized, set it to 0. Also, if using --rel-max-tick, check the use of instruction counts or simpoints to warn the user that the max tick setting does not include the checkpoint ticks.
2013-09-06ruby: network: correct naming of routersNilay Vaish
The routers are created before the network class. This results in the routers becoming children of the first link they are connected to and they get generic names like int_node and node_b. This patch creates the network object first and passes it to the topology creation function. Now the routers are children of the network object and names are much more sensible.
2013-08-26ARM: Fix configuration files for bare-metal binaries.Ali Saidi
2013-08-20ruby: add option for number of transitions per cycleNilay Vaish
The number of transitions per cycle that a controller can carry out is a proxy for the number of ports that a controller has. This value is currently 32 which is way too high. The patch introduces an option for the number of ports and uses this option in the protocol files to set the number of transitions. The default value is being set to 4. None of the se regressions change. Ruby stats for the fs regression change and are being updated.
2013-08-19config: Command line support for multi-channel memoryAndreas Hansson
This patch adds support for specifying multi-channel memory configurations on the command line, e.g. 'se/fs.py --mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it enhances the functionality of MemConfig and moves the existing makeMultiChannel class method from SimpleDRAM to the support scripts. The se/fs.py example scripts are updated to make use of the new feature.
2013-08-19mem: Change AbstractMemory defaults to match the common caseAndreas Hansson
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs.
2013-08-19config: Move the memory instantiation outside FSConfigAndreas Hansson
This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers.
2013-07-18Configs: Fix up maxtick and maxtimeJoel Hestness
This patch contains three fixes to max tick options handling in Options.py and Simulation.py: 1) Since the global simulator frequency isn't bound until m5.instantiate() is called, the maxtick resolution needs to happen after this call, since changes to the global frequency will cause m5.simulate() to misinterpret the maxtick value. Shuffling this also requires tweaking the checkpoint directory handling to signal the checkpoint restore tick back to run(). Fixing this completely and correctly will require storing the simulation frequency into checkpoints, which is beyond the scope of this patch. 2) The maxtick option in Options.py was defaulted to MaxTicks, so the old code would always skip over the maxtime part of the conditionals at the beginning of run(). Change the maxtick default to None, and set the maxtick local variable in run() appropriately. 3) To clarify whether max ticks settings are relative or absolute, split the maxtick option into separate options, for relative and absolute. Ensure that these two options and the maxtime option are handled appropriately to set the maxtick variable in Simulation.py.
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