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AgeCommit message (Expand)Author
2018-09-10configs: Use the same address ranges for dir and mem_ctrlsNikos Nikoleris
2018-09-03config: Move KVM CPU checking to CpuConfig helper moduleAndreas Sandberg
2018-08-17configs: Always exit with code 0Jason Lowe-Power
2018-07-13configs: Update the DRAM sweep script to use PyTrafficGenAndreas Sandberg
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
2018-05-16style: fix amd license and style issuesTony Gutierrez
2018-04-12configs, mem-ruby: fix issues with style in AMD licenseTony Gutierrez
2018-03-23learning_gem5: Add a simple config for MI_exampleJason Lowe-Power
2018-03-23learning_gem5: Ruby random tester files for MSIJason Lowe-Power
2018-03-23learning_gem5: Add config files for MSI protocolJason Lowe-Power
2018-03-22mem-cache: Split array indexing and replacement policies.Daniel R. Carvalho
2018-03-20arch-arm, configs: Treat the bootloader rom as cacheable memoryNikos Nikoleris
2018-03-13learning_gem5: Update README for Learning gem5Jason Lowe-Power
2018-03-06config: Switch from the print statement to the print function.Gabe Black
2018-03-02configs: Fix L3Cache instantiation in lat_mem_rd.pyNikos Nikoleris
2018-02-05config: remove dead code in fs.pyNayan Deshmukh
2018-01-29config, arm: enable device tree autogeneration for bigLITTLECurtis Dunham
2018-01-29config: Embed Device Tree generation in fs.py configGlenn Bergmans
2018-01-10configs: Fill in the cpu.isa field in etrace_replay.py since no default are p...Chen Zou
2018-01-08gpu-compute: call createThreads() on cpu objs in apu_se.pyTony Gutierrez
2018-01-02config: Handle NULL simobject parameters in read_config.py.Gabe Black
2018-01-02config: Fix parsing AddrRange parameters in read_config.py.Gabe Black
2018-01-02config: Add a --checkpoint-dir argument to read_config.py.Gabe Black
2017-12-15mem-ruby: Support atomic_noncaching acceses in rubySwapnil Haria
2017-12-12config: Fix need to set ISA of switch cpus.Austin Harris
2017-12-05config, mem, hmc: fix HMC test scriptÉder F. Zulian
2017-12-05learning_gem5: Adding code for SimpleCacheJason Lowe-Power
2017-12-05learning_gem5: Adds the simple MemObject codeJason Lowe-Power
2017-12-05learning_gem5: Add code for hello-goodbye exampleJason Lowe-Power
2017-12-05learning_gem5: Add code for simple SimObjectJason Lowe-Power
2017-11-16tests: Add tests for DRAM low power modesRadhika Jagtap
2017-11-16config: Add low power sweep for DRAMRadhika Jagtap
2017-11-13config: Fix the "script" SysPath functor.Gabe Black
2017-10-31config: Rework the SysPaths functions into functors.Gabe Black
2017-08-03configs, arm: Fix incorrect use of mem_range in bL exampleAndreas Sandberg
2017-08-03arm, config: Fix CPU names in ARM example configsAndreas Sandberg
2017-08-01arch-arm: Switch to DTOnly as the default machine typeAndreas Sandberg
2017-07-28config: Discover CPU timing models based on target ISAAndreas Sandberg
2017-07-27config, arm: SE configuration for the ARM starter kitGabor Dozsa
2017-07-27config, arm: FS configuration for the ARM starter kitGabor Dozsa
2017-07-27config, arm: Add a high-performance in order timing modelAshkan Tousi
2017-07-27config: Change mem_range attribute naming in ARM SimpleSystemGabor Dozsa
2017-07-25configs,sim-se: fix se.py multi-cpu multi-cmd issuePau Cabre
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-04config, arm: Don't import timing models for missing CPUsAndreas Sandberg
2017-07-03config: Clean up core timing model discoveryAndreas Sandberg
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
2017-07-03config: Make ex5_*.py independent of old configsAndreas Sandberg
2017-06-30config: Add missing import of 'fatal' in CpuConfigAndreas Sandberg
2017-06-30config: Make some MemConfig options optionalAndreas Sandberg