summaryrefslogtreecommitdiff
path: root/configs
AgeCommit message (Collapse)Author
2006-07-27Clean up some more config stuff.Kevin Lim
configs/common/FSConfig.py: Clean up some code to make functions look less like classes. Also put makeList function (formerly listWrapper) into m5 itself. configs/test/fs.py: Update for changed code. src/python/m5/__init__.py: Put makeList into m5. --HG-- extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
2006-07-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 45650c90385b4e13e79ccf271a30bb55552b380f
2006-07-23Fix up test.pyKevin Lim
configs/test/test.py: Fix up this config. --HG-- extra : convert_revision : e15071ee27b860cc3ad79277aa61f3e6bb7405d3
2006-07-22Reorganized SPARC binariesGabe Black
--HG-- rename : configs/test/hello_sparc => configs/test/sparc_tests/hello_sparc extra : convert_revision : d8f36fc9b346f0e89dc8406403576e88bb2dc139
2006-07-22Last minute check in. Very few functional changes other than some minor ↵Kevin Lim
config updates. Also include some recently generated stats. SConstruct: Make test CPUs option non-sticky. configs/common/FSConfig.py: Be sure to set the memory mode. configs/test/fs.py: Wrong string. tests/SConscript: Only test valid CPUs that have been compiled in. tests/test1/ref/alpha/atomic/config.ini: tests/test1/ref/alpha/atomic/config.out: tests/test1/ref/alpha/atomic/m5stats.txt: tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/config.ini: tests/test1/ref/alpha/detailed/config.out: tests/test1/ref/alpha/detailed/m5stats.txt: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/config.ini: tests/test1/ref/alpha/timing/config.out: tests/test1/ref/alpha/timing/m5stats.txt: tests/test1/ref/alpha/timing/stdout: Update output. --HG-- extra : convert_revision : 6eee2a5eae0291b5121b41bcd7021179cdd520a3
2006-07-21Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/fs.py: Hand merge. --HG-- extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
2006-07-21Rearrange the FS configs to be more shared. Also check in the full-system ↵Kevin Lim
tests. Reference stats coming soon. configs/test/fs.py: Pull out a lot of common code and put it into configs/common/FSConfig.py. --HG-- extra : convert_revision : 175b18d75f82ddecbcc9a6418fe40df314db55d5
2006-07-21Some reorganization. Options are all handled at the user level script. ↵Kevin Lim
Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs. --HG-- rename : configs/test/SysPaths.py => configs/common/SysPaths.py extra : convert_revision : 2b1b95c5f29e7ade08b1abd6f24c129d600fe2e8
2006-07-20Enforce the timing cpu ticking at it's clock rateAli Saidi
Add a max time option in seconds and a single system root clock be 1THz configs/test/fs.py: Add a max time option in seconds and a single system root clock be 1THz src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Enforce the timing cpu ticking at it's clock rate --HG-- extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
2006-07-19Update configs.Kevin Lim
configs/test/test.py: Update for changes to SEConfig. --HG-- extra : convert_revision : a089a7db4035889db01d543d9a18ea6526f832ca
2006-07-14Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/fs.py: configs/test/test.py: SCCS merged --HG-- extra : convert_revision : 7b2dbcd5881fac01dec38001c4131e73b5be52b5
2006-07-13add system.mem_mode = ['timing', 'atomic']Ali Saidi
update scripts acordingly configs/test/SysPaths.py: new syspaths from nate, this one allows you to set script, binary, and disk paths like system.dir = 'aouaou' in your script configs/test/fs.py: update for system mem_mode Put small checkpoint example Make clock 1THz configs/test/test.py: src/arch/alpha/freebsd/system.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/system.cc: src/arch/alpha/tru64/system.cc: src/arch/sparc/system.cc: src/python/m5/objects/System.py: src/sim/system.cc: src/sim/system.hh: update for system mem_mode src/dev/io_device.cc: Use time returned from sendAtomic to delay --HG-- extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge configs/test/test.py: Hand merge. --HG-- extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
2006-07-12Initial try of consolidating configuration files so they can be shared more ↵Kevin Lim
easily, especially across regression tests and simple examples. configs/test/fs.py: Pull a lot of the default options out of the config file now that they are in the Python objects themselves. Also merge this file with the single_fs.py, allowing one file to be used for both. Previously they differed only by the system they instantiated. configs/test/test.py: Initial stab at consolidating configuration files so they aren't redundant between the regression tests and the simple examples. --HG-- extra : convert_revision : e8ae3de5a6d8864831f21089d4fdb8ec690e4731
2006-07-10Migrate most of main() and and all option parsing to pythonNathan Binkert
configs/test/fs.py: configs/test/test.py: update for the new way that m5 deals with options src/python/SConscript: Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the python stuff. src/python/m5/__init__.py: redo the way options work. Move them all to main.py src/sim/main.cc: Migrate more functionality for main() into python. Namely option parsing src/python/m5/attrdict.py: A dictionary object that overrides attribute access to do item access. src/python/m5/main.py: The new location for M5's option parsing, and the main() routine to set up the simulation. --HG-- extra : convert_revision : c86b87a9f508bde1994088e23fd470c7753ee4c1
2006-07-10Update FS configs to use cpu connectors for portsRon Dreslinski
--HG-- extra : convert_revision : 1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4
2006-07-07Update cpus to use the getPort function to use a connector object to connect ↵Ron Dreslinski
the I/D cache ports to memory configs/test/test.py: Update to use new cpu getPort functionality src/cpu/base.cc: Make cpu's a memObject to expose getPort interface src/cpu/base.hh: Make cpu's a memObject to export getPort interface src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Now use the connector via getPort interface src/mem/cache/base_cache.cc: Make sure the cache recognizes all port names --HG-- extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
2006-07-06Add default responder to busAli Saidi
Update configuration for new default responder on bus Update to devices to handle their own pci config space without pciconfigall Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same bus:dev:func and interrupt Remove pciconfigspace from pci devices, and py files Add calcConfigAddr that returns address for config space based on bus/dev/function + offset configs/test/fs.py: Update configuration for new default responder on bus src/dev/ide_ctrl.cc: src/dev/ide_ctrl.hh: src/dev/ns_gige.cc: src/dev/ns_gige.hh: src/dev/pcidev.cc: src/dev/pcidev.hh: Update to handle it's own pci config space without pciconfigall src/dev/io_device.cc: src/dev/io_device.hh: change naming for pio port break out recvTiming into two functions to reuse code src/dev/pciconfigall.cc: src/dev/pciconfigall.hh: removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for src/dev/pcireg.h: add a max size for PCI config space (per PCI spec) src/dev/platform.cc: src/dev/platform.hh: remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same bus:dev:func and interrupt src/dev/sinic.cc: remove pciconfigspace as it's no longer a needed parameter src/dev/tsunami.cc: src/dev/tsunami.hh: src/dev/tsunami_pchip.cc: src/dev/tsunami_pchip.hh: add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec) src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: add idea of default responder to bus src/python/m5/objects/Pci.py: add config port for pci devices add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec) --HG-- extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9
2006-07-03Added hook to check for SMT workloads. SMT is identified by adding a ↵Korey Sewell
semicolon between the workloads. Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" -i="file1;file2" I think I am a novice python magician now!!!!.... configs/test/test.py: Added hook to check for SMT workloads. SMT is identified by adding a semicolon between the workloads. Now SMT on the O3CPU can be invoked by "/ALPHA_SE/m5.debug ../configs/test/test.py -d --cmd="hello;hello" --input="file1;file2" (btw, We are back to working for this double hello world case) I am a novice python magician now!!!!.... --HG-- extra : convert_revision : b55e10dce33f5a9dc4c78f90409ec0912bad4292
2006-06-27Add help strings for optionsAli Saidi
--HG-- extra : convert_revision : ebbafaf00c56a4d2ee65eea08a12d276f279135d
2006-06-26Merge zizzer:/bk/newmemAli Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 39c99c8acadd43f3ec42ae7550289a5075d910e4
2006-06-26add python options for input file and command line options for live processAli Saidi
--HG-- extra : convert_revision : 3db1e6d29846812378aa5174179a0686f0141580
2006-06-18use 'tick' instead of 'cycle'Korey Sewell
--HG-- extra : convert_revision : e7119d20ef95deab16081743c885979b0fa85548
2006-06-18minor device fixupsAli Saidi
configs/test/SysPaths.py: remove some tabs and add /n/poolfs/z/dist/m5/system src/dev/io_device.cc: fix since pio timing dma packts colud be nacked too src/dev/io_device.hh: move DmaReqState into DmaDevie --HG-- extra : convert_revision : 2b5300d85ab33b3753afc54bc6a04a47b6e00d20
2006-06-17Make the system paths more configurableNathan Binkert
configs/test/SysPaths.py: Make the paths more configurable --HG-- extra : convert_revision : c426b102dfe55e4b601a23e980e1b01140e0ee93
2006-06-17Add --outdir option. Didn't call it "-d" sinceSteve Reinhardt
that's already being used for "detailed cpu". Needed to add extra function for user script to pass parsed options back to m5 module. configs/test/fs.py: configs/test/test.py: Call setStandardOptions(). src/python/m5/__init__.py: Add --outdir option. Add setStandardOptions() so user script can pass parsed options back to m5 module. src/sim/main.cc: Add SWIG-wrappable function to set output dir. --HG-- extra : convert_revision : 1323bee69ca920c699a1cd1218e15b7b0875c1e5
2006-06-16Update this with the same option as single_fs.pyKevin Lim
--HG-- extra : convert_revision : 778d654f515b6af7c45165b0a9bc5ef0d60f0d19
2006-06-16Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 488b9a9965dd86ca73dc9e510e5b3122cbd357f9
2006-06-16Two updates that got combined into one ChangeSet accidentally. They're both ↵Kevin Lim
pretty simple so they shouldn't cause any trouble. First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model. Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled. SConstruct: Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled. configs/test/test.py: Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick. src/base/traceflags.py: Add in O3CPU trace flag. src/cpu/SConscript: Rename AlphaFullCPU to AlphaO3CPU. Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included. src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU. src/cpu/cpu_models.py: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model. src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/thread_state.hh: src/python/m5/objects/AlphaO3CPU.py: Rename FullCPU to O3CPU to differentiate from old FullCPU model. src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: Rename FullCPU to O3CPU to differentiate from old FullCPU model. Also #ifdef the checker code so it doesn't need to be included if it's not selected. --HG-- rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a
2006-06-15Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : 8a1cd7ff43aa4ebbfce0ff174d2f4ba3f095dd47
2006-06-15Get Port stuff working with full-system scripts.Steve Reinhardt
Key was adding support for cloning port references (trickier than it sounds). Got rid of class/instance thing and go back to instance cloning... still don't allow changing SimObject parameters/children after a class (instance) has been subclassed or instantiated (or cloned), which should avoid bizarre unintended behavior. configs/test/fs.py: Add ".port" to busses to get a port reference. Get rid of commented-out code. src/python/m5/__init__.py: resolveSimObject should call getCCObject() instead of createCCObject() to avoid cycles in recursively creating objects. src/python/m5/config.py: Get rid of class/instance thing and go back to instance cloning. Deep copy has to happen only on instance cloning then (and not on subclassing). Add getCCObject() method to force creation of C++ SimObject without recursively creating its children. Add support for cloning port references (trickier than it sounds). Also clean up some very obsolete comments. src/python/m5/objects/Bridge.py: src/python/m5/objects/Device.py: Add ports. --HG-- extra : convert_revision : 4816d05ead0de520748aace06dbd1911a33f0af8
2006-06-14tried to undo change and it didnt work so might as well put it backKorey Sewell
--HG-- extra : convert_revision : 9793917e8a3e4d30f59ff469e4f08da96ce001f9
2006-06-14change back, BK is acting upKorey Sewell
--HG-- extra : convert_revision : 11fd5ebbca0408b357e9186d1b3722eb571e874e
2006-06-14add cycle to exit messageKorey Sewell
src/arch/mips/isa/formats/trap.isa: Take out fix that tried to fix trap instruction disassembly. It forces bad compile .. configs/test/test.py: add 'cycle' to exit message --HG-- extra : convert_revision : 568877797fd2806416b4cbb388cc3f7eb2492627
2006-06-13Move SimObject creation and Port connection loopsSteve Reinhardt
into Python. Add Port and VectorPort objects and support for specifying port connections via assignment. The whole C++ ConfigNode hierarchy is gone now, as are C++ Connector objects. configs/test/fs.py: configs/test/test.py: Rewrite for new port connector syntax. src/SConscript: Remove unneeded files: - mem/connector.* - sim/config* src/dev/io_device.hh: src/mem/bridge.cc: src/mem/bridge.hh: src/mem/bus.cc: src/mem/bus.hh: src/mem/mem_object.hh: src/mem/physical.cc: src/mem/physical.hh: Allow getPort() to take an optional index to support vector ports (eventually). src/python/m5/__init__.py: Move SimObject construction and port connection operations into Python (with C++ calls). src/python/m5/config.py: Move SimObject construction and port connection operations into Python (with C++ calls). Add support for declaring and connecting MemObject ports in Python. src/python/m5/objects/Bus.py: src/python/m5/objects/PhysicalMemory.py: Add port declaration. src/sim/builder.cc: src/sim/builder.hh: src/sim/serialize.cc: src/sim/serialize.hh: ConfigNodes are gone; builder just gets the name of a .ini file section now. src/sim/main.cc: Move SimObject construction and port connection operations into Python (with C++ calls). Split remaining initialization operations into two parts, loadIniFile() and finalInit(). src/sim/param.cc: src/sim/param.hh: SimObject resolution done globally in Python now (not via ConfigNode hierarchy). src/sim/sim_object.cc: Remove unneeded #include. --HG-- extra : convert_revision : 2fa4001eaaec0c9a4231ef6e854f8e156d930dfe
2006-06-13Add in DetailedCPU to test.Kevin Lim
--HG-- extra : convert_revision : 98c67b45af239e1cf5bad6888da6577a4c3bb45d
2006-06-11Move LiveProcess::create() from arch-specific filesSteve Reinhardt
bcak to main LiveProcess, then automatically select ISA based on object file type. Now simulation scripts no longer need to care about the ISA, as they can just call LiveProcess(). configs/test/test.py: Script no longer cares about ISA. src/arch/alpha/process.cc: src/arch/alpha/process.hh: src/arch/mips/process.cc: src/arch/mips/process.hh: src/arch/sparc/process.cc: src/arch/sparc/process.hh: src/sim/process.cc: src/sim/process.hh: Move create() from arch-specific files back to main LiveProcess, then automatically select ISA based on object file type. --HG-- extra : convert_revision : ef33ffdc79623b77000f5d68edd2026760b76ab6
2006-06-10Don't allow SimObject-valued class params to be setSteve Reinhardt
after the class has been instantiated or subclassed. This is one of the main situations that leads to confusing results. configs/test/fs.py: Clean up to avoid modifying BaseCPU after it's been subclassed. --HG-- extra : convert_revision : 335cb87bc3b211ecc8969cfb99ffc28f62f1f877
2006-06-10Update scripts for testing ALPHA_FS and MIPS_SE.Steve Reinhardt
Minor fixes to ALPHA_FS and SPARC_SE. SPARC_SE still does not compile... looks like there are unresolved issues with ExecContext -> ThreadContext rename/reorg. configs/test/fs.py: Port to new script interface/model. configs/test/test.py: Add support for running MIPS test(s) too via command-line option. src/arch/alpha/ev5.cc: Fix include file. src/arch/sparc/regfile.hh: Make Bit64 a ULL constant to avoid compiler error. --HG-- extra : convert_revision : c46c179758271c4f00171faaa579915846bf4624
2006-06-09Move main control from C++ into Python.Steve Reinhardt
User script now invokes initialization and simulation loop after building configuration. These functions are exported from C++ to Python using SWIG. SConstruct: Set up SWIG builder & scanner. Set up symlinking of source files into build directory (by not disabling the default behavior). configs/test/test.py: Rewrite to use new script-driven interface. Include a sample option. src/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). Add SWIG-generated main_wrap.cc to source list. src/arch/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/trace/opt_cpu.cc: src/cpu/trace/trace_cpu.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: src/sim/serialize.cc: src/sim/syscall_emul.cc: SimExit() is now exitSimLoop(). src/cpu/base.cc: SimExitEvent is now SimLoopExitEvent src/python/SConscript: Add SWIG build command for main.i. Use python/m5 in build dir as source for zip archive... easy now with file duplication enabled. src/python/m5/__init__.py: - Move copyright notice back to C++ so we can print it right away, even for interactive sessions. - Get rid of argument parsing code; just provide default option descriptors for user script to call optparse with. - Don't clutter m5 namespace by sucking in all of m5.config and m5.objects. - Move instantiate() function here from config.py. src/python/m5/config.py: - Move instantiate() function to __init__.py. - Param.Foo deferred type lookups must use m5.objects namespace now (not m5). src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/AlphaFullCPU.py: src/python/m5/objects/AlphaTLB.py: src/python/m5/objects/BadDevice.py: src/python/m5/objects/BaseCPU.py: src/python/m5/objects/BaseCache.py: src/python/m5/objects/Bridge.py: src/python/m5/objects/Bus.py: src/python/m5/objects/CoherenceProtocol.py: src/python/m5/objects/Device.py: src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/IntrControl.py: src/python/m5/objects/MemObject.py: src/python/m5/objects/MemTest.py: src/python/m5/objects/Pci.py: src/python/m5/objects/PhysicalMemory.py: src/python/m5/objects/Platform.py: src/python/m5/objects/Process.py: src/python/m5/objects/Repl.py: src/python/m5/objects/Root.py: src/python/m5/objects/SimConsole.py: src/python/m5/objects/SimpleDisk.py: src/python/m5/objects/System.py: src/python/m5/objects/Tsunami.py: src/python/m5/objects/Uart.py: Fix up imports (m5 namespace no longer includes m5.config). src/sim/eventq.cc: src/sim/eventq.hh: Support for Python-called simulate() function: - Use IsExitEvent flag to signal events that want to exit the simulation loop gracefully (instead of calling exit() to terminate the process). - Modify interface to hand exit event object back to caller so it can be inspected for cause. src/sim/host.hh: Add MaxTick constant. src/sim/main.cc: Move copyright notice back to C++ so we can print it right away, even for interactive sessions. Use PYTHONPATH environment var to set module path (instead of clunky code injection method). Move main control from here into Python: - Separate initialization code and simulation loop into separate functions callable from Python. - Make Python interpreter invocation more pure (more like directly invoking interpreter). Add -i and -p flags (only options on binary itself; other options processed by Python). Import readline package when using interactive mode. src/sim/sim_events.cc: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). src/sim/sim_events.hh: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). Get rid of a few unused constructors. src/sim/sim_exit.hh: SimExit() is now exitSimLoop(). Get rid of unused functions. Add comments. --HG-- extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
2006-05-17Get basic full-system working with AtomicSimpleCPU.Steve Reinhardt
SConscript: Comment out sinic for now... needs to be fixed to compile under newmem. configs/test/SysPaths.py: Fix paths. configs/test/fs.py: SimpleCPU -> AtomicSimpleCPU Fix vmlinux path cpu/simple/atomic.cc: Fix suspendContext() so quiesce works. Don't forget to checkForInterrupts(). cpu/simple/base.cc: Minor fix to interrupt check code. dev/ide_disk.hh: Don't declare regStats() in header since it's not in .cc file anymore (will need to add it back in when stats are added back). dev/io_device.cc: Set packet dest to Packet::Broadcast. dev/pciconfigall.cc: Set PCI config packet result to Success. python/m5/objects/Root.py: Add debug object to Root so things like break_cycles can be set from command line. --HG-- extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
2006-05-16Split SimpleCPU into two different models, AtomicSimpleCPU andSteve Reinhardt
TimingSimpleCPU, which use atomic and timing memory accesses respectively. Common code is factored into the BaseSimpleCPU class. AtomicSimpleCPU includes an option (simulate_stalls) to add delays based on the estimated latency reported by the atomic accesses. Plain old "SimpleCPU" is gone; I have not updated all the config files (just test/test.py). Also fixes to get timing accesses working in new memory model and to get split-phase memory instruction definitions working with new memory model as well. arch/alpha/isa/main.isa: Need to include packet_impl.h for functions that use Packet objects. arch/alpha/isa/mem.isa: Change completeAcc() methods to take Packet object pointers. Also split out StoreCond template for completeAcc(), since that's the only one that needs write_result and we get an unused variable warning if we always have it in there. build/SConstruct: Update list of recognized CPU model names. configs/test/test.py: Change SimpleCPU to AtomicSimpleCPU. cpu/SConscript: Define sources for new CPU models. Add split memory access methods to CPU model signatures. cpu/cpu_models.py: cpu/static_inst.hh: Define new CPU models. cpu/simple/base.cc: cpu/simple/base.hh: Factor out pieces specific to Atomic or Timing models. mem/bus.cc: Bus needs to be able to route timing packets based on explicit dest so responses can get back to requester. Set dest to Packet::Broadcast to indicate that dest should be derived from address. Also set packet src field based on port from which packet is sent. mem/bus.hh: Set packet src field based on port from which packet is sent. mem/packet.hh: Define Broadcast destination address to indicate that packet should be routed based on address. mem/physical.cc: Set packet dest on response so packet is routed back to requester properly. mem/port.cc: Flag blob packets as Broadcast. python/m5/objects/PhysicalMemory.py: Change default latency to be 1 cycle. --HG-- rename : cpu/simple/cpu.cc => cpu/simple/base.cc rename : cpu/simple/cpu.hh => cpu/simple/base.hh extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
2006-05-07Minor changes for FP ... MIPS now works for floating-point programs...Korey Sewell
Now we are to the point where more benchmarks and instruction-coverage is necessary to totally verify/validate correct operation across all MIPS instructions arch/mips/isa_traits.hh: fix for reading double values ... must rearrange bits before using void* to read double. configs/test/hello_mips: real hello world MIPS binary --HG-- extra : convert_revision : 153de1f8a830882c6972bd0bdb56da818f614def
2006-05-04Merge zizzer:/bk/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem --HG-- extra : convert_revision : c48a8857f5a520ff8061eb3d8f08dcd43661e68c
2006-05-02Redo the FloatRegFile using unsigned integersKorey Sewell
Edit the convert_and_round function which access FloatRegFile arch/isa_parser.py: recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately arch/mips/isa/decoder.isa: Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the bit manipulation ourselves. We can just concern ourselves with values. Use unsigned double to get movd... arch/mips/isa/formats/fp.isa: float debug statement arch/mips/isa_traits.cc: add different versions of convert_and_round functions arch/mips/isa_traits.hh: Use an array of uint32_t unsigned integers to represent the Floating Point Regfile configs/test/hello_mips: basic FP program cpu/simple/cpu.hh: spacing --HG-- extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
2006-04-28Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : d6f7c4dd146613eeba39249f2d916a77108bc8c1
2006-04-28random mix of tidbitsAli Saidi
configs/test/fs.py: update fs.py to use a bus bridge cpu/simple/cpu.hh: cpu should just return that it doesn't snoop any address ranges python/m5/objects/System.py: move boot_osflags to system --HG-- extra : convert_revision : b4256df7eada7e65b69513361de8bffc3fdd680b
2006-04-28Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem cpu/simple/cpu.cc: Hand merged --HG-- extra : convert_revision : 68414730c23d41c30cfb7bcfa604029a5fc8622c
2006-04-28Changed the hello_sparc executable back to the cross compiled oneGabe Black
--HG-- extra : convert_revision : 565f75f76dd26ca0e25de4c89d1597a9f39483fd
2006-04-24Mostly done with all device models for new memory system. Still need to get ↵Ali Saidi
timing packets working and get sinic working after merge from head. Checkpointing may need some work now. Endian-happiness still not complete. SConscript: add all devices back into make file base/inet.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/pktfifo.cc: dev/pktfifo.hh: rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system configs/test/fs.py: add nics to fs.py cpu/cpu_exec_context.cc: remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the static virtual ports in the exec context cpu/simple/cpu.cc: cpu/simple/cpu.hh: dev/alpha_console.cc: dev/ide_ctrl.cc: use new methods for accessing packet data dev/ide_disk.cc: add some more dprintfs dev/io_device.cc: delete packets when we are done with them. Update for new packet methods to access data dev/isa_fake.cc: dev/pciconfigall.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart8250.cc: dev/uart8250.hh: mem/physical.cc: mem/port.cc: dUpdate for new packet methods to access data dev/ns_gige.cc: Update for new memory system dev/ns_gige.hh: python/m5/objects/Ethernet.py: update for new memory system dev/sinic.cc: dev/sinic.hh: Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions mem/packet.hh: Add methods to access data instead of accessing it directly. --HG-- extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e