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Author
2012-10-30
config: Unify caches used in regressions and adjust L2 MSHRs
Andreas Hansson
2012-10-27
ruby: set the is_icache param for caches
Malek Musleh
2012-10-27
Ruby: Use block size in configuring directory bits in address
Jason Power ext:(%2C%20Joel%20Hestness%20%3Chestness%40cs.wisc.edu%3E)
2012-10-26
config: Add a check for fastmem only used with Atomic CPU
Andreas Hansson
2012-10-26
config: Remove unused mem_size in fs.py
Andreas Hansson
2012-10-26
config: Fix the cache class naming in regression scripts
Andreas Hansson
2012-10-25
config: Use SimpleDRAM in full-system, and with o3 and inorder
Andreas Hansson
2012-10-25
config: Use shared cache config for regressions
Andreas Hansson
2012-10-15
ruby: improved support for functional accesses
Nilay Vaish
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-10-15
Regression: Use CPU clock and 32-byte width for L1-L2 bus
Andreas Hansson
2012-10-02
ruby: changes to simple network
Nilay Vaish
2012-09-28
Configs: SE script fix for Alpha and Ruby simulations
Malek Musleh
2012-09-27
Configs: Fix memtest cache latency to match new parameters
Andreas Hansson
2012-09-27
Configs: Fix memtest.py by moving the system port
Andreas Hansson
2012-09-25
Cache: add a response latency to the caches
Mrinmoy Ghosh
2012-09-19
AddrRange: Simplify AddrRange params Python hierarchy
Andreas Hansson
2012-09-12
se.py Ruby: Connect TLB walker ports
Joel Hestness
2012-09-12
Standard Switch: Drain the system before switching CPUs
Joel Hestness
2012-09-11
se.py: removes error in passing options to a binary
Nilay Vaish
2012-09-11
Checkpoint: Pass maxtick to avoid undefined variable
Andreas Hansson
2012-09-09
se.py: support specifying multiple programs via command line
Nilay Vaish
2012-08-22
Bridge: Remove NACKs in the bridge and unify with packet queue
Andreas Hansson
2012-08-21
Checkpoint: Fix broken checkpointing functionality
Andreas Hansson
2012-08-16
Ruby: Add RubySystem parameter to MemoryControl
Jason Power
2012-08-15
configs: add option for repeatedly switching back-and-forth between cpu types.
Anthony Gutierrez
2012-08-10
Ruby: Clean up topology changes
Jason Power
2012-08-06
Simulation.py: move code related to checkpointing to functions
Nilay Vaish
2012-08-06
Config: change how cpu class is set
Nilay Vaish
2012-07-23
Config: Use clock option in se/fs script and pass to switch_cpus
Andreas Hansson
2012-07-12
Mem: Make SimpleMemory single ported
Andreas Hansson
2012-07-10
ruby: remove the cpu assumptions for the random tester
Brad Beckmann
2012-07-10
ruby: changes how Topologies are created
Brad Beckmann
2012-06-11
configs: add run scripts for ics/gb versions of android and bbench
Anthony Gutierrez
2012-06-07
Config: call to setWorkCountOptions() for all ISAs
Nilay Vaish
2012-06-07
Config: Remove setMipsOptions
Nilay Vaish
2012-06-07
Config: changes to a couple of error msgs
Nilay Vaish
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-05-16
Config: Fix a typo in the se.py script for setting fastmem
Andreas Hansson
2012-05-03
Config: Fix help msg for option --mem-size
Jayneel Gandhi
2012-04-17
SE Config: Changed se.py to support multithreaded mode
Jayneel Gandhi
2012-04-16
Config: Add command line options for disk image and memory size
Jayneel Gandhi
2012-04-06
ruby: set SimpleTiming as the default cpu
Brad Beckmann
2012-04-06
rubytest: seperated read and write ports.
Brad Beckmann
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
2012-04-05
Config: corrects the way Ruby attaches to the DMA ports
Nilay Vaish
2012-04-05
Ruby: Fix the example configurations option parsing
Andreas Hansson
2012-04-03
Atomic: Remove the physmem_port and access memory directly
Andreas Hansson
2012-03-30
Ruby: Remove the physMemPort and instead access memory directly
Andreas Hansson
2012-03-28
Config: Change the way options are added
Nilay Vaish
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