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2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to ↵Ali Saidi
non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-02-24Configs: Explicitly import env in Benchmarks.pyGabe Black
env was being implicitly imported into Benchmarks.py through SysPaths.py. This change brings it in explicitly in the file where it's used.
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
2011-02-23configs: cache: add cache line size optionKorey Sewell
2011-02-23configs: set default cache paramsKorey Sewell
It's confusing (especially to new users), when you are setting some standard parameters (as defined in Options.py) and they aren't reflected in the simulations so we might as well link the settings in CacheConfig.py to those in Options.py
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-08memtest: due to contention increase, increased deadlock thresholdBrad Beckmann
2011-02-08config: fixed minor bug connecting dma devices to rubyBrad Beckmann
2011-02-07X86, Config: Move the setting of work count options to a separate function.Gabe Black
This way things that don't care about work count options and/or aren't called by something that has those command line options set up doesn't have to build a fake object to carry in inert values.
2011-02-06boot: script that creates a checkpoint after Linux boot upBrad Beckmann
2011-02-06ruby: numa bit fix for sparse memoryBrad Beckmann
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06ruby: x86 fs config supportBrad Beckmann
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann
2011-02-03Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
2011-02-02X86: Change how the default disk image gets set up.Gabe Black
The disk image to use was always being forced to a particular value. This change changes what disk image is selected as the default based on the architecture being built. In the future, a more sophisticated system might be used that selected a path based on certain rules instead of relying on one off file names.
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
M5 skips over any simulated time where it doesn't have any work to do. When the simulation is active, the time skipped is short and the work done at any point in time is relatively substantial. If the time between events is long and/or the work to do at each event is small, it's possible for simulated time to pass faster than real time. When running a benchmark that can be good because it means the simulation will finish sooner in real time. When interacting with the real world through, for instance, a serial terminal or bridge to a real network, this can be a problem. Human or network response time could be greatly exagerated from the perspective of the simulation and make simulated events happen "too soon" from an external perspective. This change adds the capability to force the simulation to run no faster than real time. It does so by scheduling a periodic event that checks to see if its simulated period is shorter than its real period. If it is, it stalls the simulation until they're equal. This is called time syncing. A future change could add pseudo instructions which turn time syncing on and off from within the simulation. That would allow time syncing to be used for the interactive parts of a session but then turned off when running a benchmark using the m5 utility program inside a script. Time syncing would probably not happen anyway while running a benchmark because there would be plenty of work for M5 to do, but the event overhead could be avoided.
2011-01-10ruby: get rid of ruby's Debug.hhNathan Binkert
Get rid of the Debug class Get rid of ASSERT and use assert Use DPRINTFR for ProtocolTrace
2011-01-03Ruby: Add option for random seed to Ruby.pyNilay Vaish
This patch adds an option to the script Ruby.py for setting the parameter m_random_seed used for randomizing delays in the memory system. The option can be specified as "--random_seed <seed value>".
2010-12-07Configs: Automatically choose the correct hello world binary.Ali Saidi
2010-11-17Config: Change misleading "cycle" message to say "tick".Gabe Black
Most of the messages in the config scripts that report a time value already print "@ tick" followed by the current tick value, but a few were printing "@ cycle". Since this is a distinction that's frequently confusing to new users, this changes those message to the more accurate and consistent "@ tick".
2010-11-15ARM: Add support for a dumb IDE controllerAli Saidi
2010-11-08Mem: Finish half-baked support for mmaping file in physmem.Ali Saidi
Physmem has a parameter to be able to mem map a file, however it isn't actually used. This changeset utilizes the parameter so a file can be mmapped.
2010-10-22Configs: Stop setting the "mem" parameter in splash2 config files.Gabe Black
This parameter is no longer used, and trying to set it like these scripts were gives a simobject two parents and causes the simulation to die.
2010-08-30config: fixed numa high bit setting bugBrad Beckmann
2010-08-30config: minor fix to probe filter index settingBrad Beckmann
2010-08-29ruby: None, not noneNathan Binkert
2010-08-25memtest: scale associativity and mshrs according to configSteve Reinhardt
Use the actual fanouts in the tree specification to scale cache associativity and mshrs instead of dumb constants.
2010-08-24config: changed ruby config file names to be consistentBrad Beckmann
2010-08-24config: remove ruby's requirement on the timing cmd line paramBrad Beckmann
Since ruby only works in timing mode, explicitly requiring the timing cmd line param to be specified is not necessary.
2010-08-24config: fixed ruby dma device connectionsBrad Beckmann
2010-08-24testers: move testers to a new directoryBrad Beckmann
This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-23ARM: Add configuration for Linux/Full SystemAli Saidi
2010-08-20ruby: Recycle latency fix for hammerBrad Beckmann
Patch allows each individual message buffer to have different recycle latencies and allows the overall recycle latency to be specified at the cmd line. The patch also adds profiling info to make sure no one processor's requests are recycled too much.
2010-08-20ruby: added probe filter support to hammerBrad Beckmann
2010-08-20ruby: fixed DirectoryMemory's numa_high_bit configurationBrad Beckmann
This fix includes the off-by-one bit selection bug for numa mapping.
2010-08-20ruby: Disable migratory sharing for token and hammerBrad Beckmann
This patch allows one to disable migratory sharing for those cache blocks that are accessed by atomic requests. While the implementations are different between the token and hammer protocols, the motivation is the same. For Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that have been locked by LL accesses. Therefore, locked blocks should not transfer write permissions when responding to these load requests. Instead, only they only transfer read permissions so that the subsequent SC access can possibly succeed.
2010-08-20ruby: Improved try except blocks in ruby creationBrad Beckmann
Replaced the sys.exit in the try-except blocks with raise so that the python call stack will be printed
2010-08-20config: added cmd options to control ruby debugBrad Beckmann
2010-08-20ruby: Resurrected Ruby's deterministic testsBrad Beckmann
Added the request series and invalidate deterministic tests as new cpu models and removed the no longer needed ruby tests --HG-- rename : configs/example/rubytest.py => configs/example/determ_test.py rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/DirectedGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/DirectedGenerator.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/InvalidateGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/InvalidateGenerator.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/directedtest/RubyDirectedTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/directedtest/RubyDirectedTester.hh rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/SeriesRequestGenerator.cc rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/SeriesRequestGenerator.hh
2010-08-20ruby: Reduced ruby latenciesBrad Beckmann
The previous slower ruby latencies created a mismatch between the faster M5 cpu models and the much slower ruby memory system. Specifically smp interrupts were much slower and infrequent, as well as cpus moving in and out of spin locks. The result was many cpus were idle for large periods of time. These changes fix the latency mismatch.
2010-08-20memtest: Memtester support for DMABrad Beckmann
This patch adds DMA testing to the Memtester and is inherits many changes from Polina's old tester_dma_extension patch. Since Ruby does not work in atomic mode, the atomic mode options are removed.
2010-08-20config: Improve ruby simobject namesBrad Beckmann
This patch attaches ruby objects to the system before the topology is created so that their simobject names read their meaningful variable names instead of their topology name.
2010-08-20ruby: added token broadcast config params to cmd optionsBrad Beckmann
2010-08-20config: reorganized how ruby specifies command-line optionsBrad Beckmann
2010-08-20config: moved python protocol config filesBrad Beckmann
Moved the python protocol config files back to their original location to avoid addToPath calls. --HG-- rename : configs/ruby/protocols/MESI_CMP_directory.py => configs/ruby/MESI_CMP_directory.py rename : configs/ruby/protocols/MI_example.py => configs/ruby/MI_example.py rename : configs/ruby/protocols/MOESI_CMP_directory.py => configs/ruby/MOESI_CMP_directory.py rename : configs/ruby/protocols/MOESI_CMP_token.py => configs/ruby/MOESI_CMP_token.py rename : configs/ruby/protocols/MOESI_hammer.py => configs/ruby/MOESI_hammer.py
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
Meant to add these with the previous batch of csets.
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
The separate restoreCheckpoint() call is gone; just pass the checkpoint dir as an optional arg to instantiate(). This change is a precursor to some more extensive reworking of the startup code.
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